traffic.tan.qmsg

一些Verilog学习程序A

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register numb\[4\] register numb\[4\] 237.42 MHz 4.212 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 237.42 MHz between source register \"numb\[4\]\" and destination register \"numb\[4\]\" (period= 4.212 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.948 ns + Longest register register " "Info: + Longest register to register delay is 3.948 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns numb\[4\] 1 REG LCFF_X13_Y12_N21 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X13_Y12_N21; Fanout = 6; REG Node = 'numb\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { numb[4] } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.477 ns) + CELL(0.534 ns) 1.011 ns Equal2~100 2 COMB LCCOMB_X13_Y12_N10 2 " "Info: 2: + IC(0.477 ns) + CELL(0.534 ns) = 1.011 ns; Loc. = LCCOMB_X13_Y12_N10; Fanout = 2; COMB Node = 'Equal2~100'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.011 ns" { numb[4] Equal2~100 } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.378 ns) + CELL(0.206 ns) 1.595 ns Equal2~101 3 COMB LCCOMB_X13_Y12_N2 2 " "Info: 3: + IC(0.378 ns) + CELL(0.206 ns) = 1.595 ns; Loc. = LCCOMB_X13_Y12_N2; Fanout = 2; COMB Node = 'Equal2~101'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.584 ns" { Equal2~100 Equal2~101 } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.386 ns) + CELL(0.206 ns) 2.187 ns numb\[0\]~1495 4 COMB LCCOMB_X13_Y12_N30 5 " "Info: 4: + IC(0.386 ns) + CELL(0.206 ns) = 2.187 ns; Loc. = LCCOMB_X13_Y12_N30; Fanout = 5; COMB Node = 'numb\[0\]~1495'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.592 ns" { Equal2~101 numb[0]~1495 } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.389 ns) + CELL(0.206 ns) 2.782 ns numb\[4\]~1505 5 COMB LCCOMB_X13_Y12_N18 4 " "Info: 5: + IC(0.389 ns) + CELL(0.206 ns) = 2.782 ns; Loc. = LCCOMB_X13_Y12_N18; Fanout = 4; COMB Node = 'numb\[4\]~1505'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.595 ns" { numb[0]~1495 numb[4]~1505 } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.344 ns) + CELL(0.822 ns) 3.948 ns numb\[4\] 6 REG LCFF_X13_Y12_N21 6 " "Info: 6: + IC(0.344 ns) + CELL(0.822 ns) = 3.948 ns; Loc. = LCFF_X13_Y12_N21; Fanout = 6; REG Node = 'numb\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.166 ns" { numb[4]~1505 numb[4] } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.974 ns ( 50.00 % ) " "Info: Total cell delay = 1.974 ns ( 50.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.974 ns ( 50.00 % ) " "Info: Total interconnect delay = 1.974 ns ( 50.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.948 ns" { numb[4] Equal2~100 Equal2~101 numb[0]~1495 numb[4]~1505 numb[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.948 ns" { numb[4] Equal2~100 Equal2~101 numb[0]~1495 numb[4]~1505 numb[4] } { 0.000ns 0.477ns 0.378ns 0.386ns 0.389ns 0.344ns } { 0.000ns 0.534ns 0.206ns 0.206ns 0.206ns 0.822ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.765 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.765 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns CLK 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns CLK~clkctrl 2 COMB CLKCTRL_G2 31 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 31; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.143 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.856 ns) + CELL(0.666 ns) 2.765 ns numb\[4\] 3 REG LCFF_X13_Y12_N21 6 " "Info: 3: + IC(0.856 ns) + CELL(0.666 ns) = 2.765 ns; Loc. = LCFF_X13_Y12_N21; Fanout = 6; REG Node = 'numb\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.522 ns" { CLK~clkctrl numb[4] } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 63.87 % ) " "Info: Total cell delay = 1.766 ns ( 63.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.999 ns ( 36.13 % ) " "Info: Total interconnect delay = 0.999 ns ( 36.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.765 ns" { CLK CLK~clkctrl numb[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.765 ns" { CLK CLK~combout CLK~clkctrl numb[4] } { 0.000ns 0.000ns 0.143ns 0.856ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.765 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.765 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns CLK 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns CLK~clkctrl 2 COMB CLKCTRL_G2 31 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 31; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.143 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.856 ns) + CELL(0.666 ns) 2.765 ns numb\[4\] 3 REG LCFF_X13_Y12_N21 6 " "Info: 3: + IC(0.856 ns) + CELL(0.666 ns) = 2.765 ns; Loc. = LCFF_X13_Y12_N21; Fanout = 6; REG Node = 'numb\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.522 ns" { CLK~clkctrl numb[4] } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 63.87 % ) " "Info: Total cell delay = 1.766 ns ( 63.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.999 ns ( 36.13 % ) " "Info: Total interconnect delay = 0.999 ns ( 36.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.765 ns" { CLK CLK~clkctrl numb[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.765 ns" { CLK CLK~combout CLK~clkctrl numb[4] } { 0.000ns 0.000ns 0.143ns 0.856ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.765 ns" { CLK CLK~clkctrl numb[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.765 ns" { CLK CLK~combout CLK~clkctrl numb[4] } { 0.000ns 0.000ns 0.143ns 0.856ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.765 ns" { CLK CLK~clkctrl numb[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.765 ns" { CLK CLK~combout CLK~clkctrl numb[4] } { 0.000ns 0.000ns 0.143ns 0.856ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 113 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 113 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.948 ns" { numb[4] Equal2~100 Equal2~101 numb[0]~1495 numb[4]~1505 numb[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.948 ns" { numb[4] Equal2~100 Equal2~101 numb[0]~1495 numb[4]~1505 numb[4] } { 0.000ns 0.477ns 0.378ns 0.386ns 0.389ns 0.344ns } { 0.000ns 0.534ns 0.206ns 0.206ns 0.206ns 0.822ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.765 ns" { CLK CLK~clkctrl numb[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.765 ns" { CLK CLK~combout CLK~clkctrl numb[4] } { 0.000ns 0.000ns 0.143ns 0.856ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.765 ns" { CLK CLK~clkctrl numb[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.765 ns" { CLK CLK~combout CLK~clkctrl numb[4] } { 0.000ns 0.000ns 0.143ns 0.856ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "LAMPB\[0\]~reg0 EN CLK 8.111 ns register " "Info: tsu for register \"LAMPB\[0\]~reg0\" (data pin = \"EN\", clock pin = \"CLK\") is 8.111 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.916 ns + Longest pin register " "Info: + Longest pin to register delay is 10.916 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns EN 1 PIN PIN_126 23 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_126; Fanout = 23; PIN Node = 'EN'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.053 ns) + CELL(0.651 ns) 8.638 ns LAMPB\[3\]~193 2 COMB LCCOMB_X8_Y8_N8 7 " "Info: 2: + IC(7.053 ns) + CELL(0.651 ns) = 8.638 ns; Loc. = LCCOMB_X8_Y8_N8; Fanout = 7; COMB Node = 'LAMPB\[3\]~193'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.704 ns" { EN LAMPB[3]~193 } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.423 ns) + CELL(0.855 ns) 10.916 ns LAMPB\[0\]~reg0 3 REG LCFF_X12_Y12_N29 3 " "Info: 3: + IC(1.423 ns) + CELL(0.855 ns) = 10.916 ns; Loc. = LCFF_X12_Y12_N29; Fanout = 3; REG Node = 'LAMPB\[0\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.278 ns" { LAMPB[3]~193 LAMPB[0]~reg0 } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.440 ns ( 22.35 % ) " "Info: Total cell delay = 2.440 ns ( 22.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.476 ns ( 77.65 % ) " "Info: Total interconnect delay = 8.476 ns ( 77.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.916 ns" { EN LAMPB[3]~193 LAMPB[0]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.916 ns" { EN EN~combout LAMPB[3]~193 LAMPB[0]~reg0 } { 0.000ns 0.000ns 7.053ns 1.423ns } { 0.000ns 0.934ns 0.651ns 0.855ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 113 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.765 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.765 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns CLK 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns CLK~clkctrl 2 COMB CLKCTRL_G2 31 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 31; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.143 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.856 ns) + CELL(0.666 ns) 2.765 ns LAMPB\[0\]~reg0 3 REG LCFF_X12_Y12_N29 3 " "Info: 3: + IC(0.856 ns) + CELL(0.666 ns) = 2.765 ns; Loc. = LCFF_X12_Y12_N29; Fanout = 3; REG Node = 'LAMPB\[0\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.522 ns" { CLK~clkctrl LAMPB[0]~reg0 } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 63.87 % ) " "Info: Total cell delay = 1.766 ns ( 63.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.999 ns ( 36.13 % ) " "Info: Total interconnect delay = 0.999 ns ( 36.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.765 ns" { CLK CLK~clkctrl LAMPB[0]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.765 ns" { CLK CLK~combout CLK~clkctrl LAMPB[0]~reg0 } { 0.000ns 0.000ns 0.143ns 0.856ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.916 ns" { EN LAMPB[3]~193 LAMPB[0]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.916 ns" { EN EN~combout LAMPB[3]~193 LAMPB[0]~reg0 } { 0.000ns 0.000ns 7.053ns 1.423ns } { 0.000ns 0.934ns 0.651ns 0.855ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.765 ns" { CLK CLK~clkctrl LAMPB[0]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.765 ns" { CLK CLK~combout CLK~clkctrl LAMPB[0]~reg0 } { 0.000ns 0.000ns 0.143ns 0.856ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK BCOUNT\[1\] numb\[1\] 8.848 ns register " "Info: tco from clock \"CLK\" to destination pin \"BCOUNT\[1\]\" through register \"numb\[1\]\" is 8.848 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.765 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.765 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns CLK 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns CLK~clkctrl 2 COMB CLKCTRL_G2 31 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 31; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.143 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.856 ns) + CELL(0.666 ns) 2.765 ns numb\[1\] 3 REG LCFF_X13_Y12_N1 7 " "Info: 3: + IC(0.856 ns) + CELL(0.666 ns) = 2.765 ns; Loc. = LCFF_X13_Y12_N1; Fanout = 7; REG Node = 'numb\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.522 ns" { CLK~clkctrl numb[1] } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 63.87 % ) " "Info: Total cell delay = 1.766 ns ( 63.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.999 ns ( 36.13 % ) " "Info: Total interconnect delay = 0.999 ns ( 36.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.765 ns" { CLK CLK~clkctrl numb[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.765 ns" { CLK CLK~combout CLK~clkctrl numb[1] } { 0.000ns 0.000ns 0.143ns 0.856ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 113 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.779 ns + Longest register pin " "Info: + Longest register to pin delay is 5.779 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns numb\[1\] 1 REG LCFF_X13_Y12_N1 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X13_Y12_N1; Fanout = 7; REG Node = 'numb\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { numb[1] } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.553 ns) + CELL(3.226 ns) 5.779 ns BCOUNT\[1\] 2 PIN PIN_58 0 " "Info: 2: + IC(2.553 ns) + CELL(3.226 ns) = 5.779 ns; Loc. = PIN_58; Fanout = 0; PIN Node = 'BCOUNT\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.779 ns" { numb[1] BCOUNT[1] } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.226 ns ( 55.82 % ) " "Info: Total cell delay = 3.226 ns ( 55.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.553 ns ( 44.18 % ) " "Info: Total interconnect delay = 2.553 ns ( 44.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.779 ns" { numb[1] BCOUNT[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.779 ns" { numb[1] BCOUNT[1] } { 0.000ns 2.553ns } { 0.000ns 3.226ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.765 ns" { CLK CLK~clkctrl numb[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.765 ns" { CLK CLK~combout CLK~clkctrl numb[1] } { 0.000ns 0.000ns 0.143ns 0.856ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.779 ns" { numb[1] BCOUNT[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.779 ns" { numb[1] BCOUNT[1] } { 0.000ns 2.553ns } { 0.000ns 3.226ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "numb\[1\] EN CLK -4.542 ns register " "Info: th for register \"numb\[1\]\" (data pin = \"EN\", clock pin = \"CLK\") is -4.542 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.765 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.765 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns CLK 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns CLK~clkctrl 2 COMB CLKCTRL_G2 31 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 31; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.143 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.856 ns) + CELL(0.666 ns) 2.765 ns numb\[1\] 3 REG LCFF_X13_Y12_N1 7 " "Info: 3: + IC(0.856 ns) + CELL(0.666 ns) = 2.765 ns; Loc. = LCFF_X13_Y12_N1; Fanout = 7; REG Node = 'numb\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.522 ns" { CLK~clkctrl numb[1] } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 63.87 % ) " "Info: Total cell delay = 1.766 ns ( 63.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.999 ns ( 36.13 % ) " "Info: Total interconnect delay = 0.999 ns ( 36.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.765 ns" { CLK CLK~clkctrl numb[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.765 ns" { CLK CLK~combout CLK~clkctrl numb[1] } { 0.000ns 0.000ns 0.143ns 0.856ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 113 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.613 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.613 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns EN 1 PIN PIN_126 23 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_126; Fanout = 23; PIN Node = 'EN'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.957 ns) + CELL(0.614 ns) 7.505 ns numb\[1\]~1499 2 COMB LCCOMB_X13_Y12_N0 1 " "Info: 2: + IC(5.957 ns) + CELL(0.614 ns) = 7.505 ns; Loc. = LCCOMB_X13_Y12_N0; Fanout = 1; COMB Node = 'numb\[1\]~1499'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.571 ns" { EN numb[1]~1499 } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.613 ns numb\[1\] 3 REG LCFF_X13_Y12_N1 7 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.613 ns; Loc. = LCFF_X13_Y12_N1; Fanout = 7; REG Node = 'numb\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { numb[1]~1499 numb[1] } "NODE_NAME" } } { "traffic.v" "" { Text "F:/Verilog/绿灯、黄灯和红灯/traffic.v" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.656 ns ( 21.75 % ) " "Info: Total cell delay = 1.656 ns ( 21.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.957 ns ( 78.25 % ) " "Info: Total interconnect delay = 5.957 ns ( 78.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.613 ns" { EN numb[1]~1499 numb[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.613 ns" { EN EN~combout numb[1]~1499 numb[1] } { 0.000ns 0.000ns 5.957ns 0.000ns } { 0.000ns 0.934ns 0.614ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.765 ns" { CLK CLK~clkctrl numb[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.765 ns" { CLK CLK~combout CLK~clkctrl numb[1] } { 0.000ns 0.000ns 0.143ns 0.856ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.613 ns" { EN numb[1]~1499 numb[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.613 ns" { EN EN~combout numb[1]~1499 numb[1] } { 0.000ns 0.000ns 5.957ns 0.000ns } { 0.000ns 0.934ns 0.614ns 0.108ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}