traffic.map.rpt

一些Verilog学习程序A

; countb.011 ; 0          ; 0          ; 1          ; 1          ; 0          ;
; countb.010 ; 0          ; 1          ; 0          ; 1          ; 0          ;
; countb.100 ; 0          ; 0          ; 0          ; 1          ; 1          ;
; countb.001 ; 1          ; 0          ; 0          ; 1          ; 0          ;
+------------+------------+------------+------------+------------+------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 31    ;
; Number of registers using Synchronous Clear  ; 4     ;
; Number of registers using Synchronous Load   ; 10    ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 17    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; LAMPA[3]~reg0                          ; 6       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |traffic|LAMPA[0]~reg0     ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |traffic|LAMPB[3]~reg0     ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |traffic|numa[7]           ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |traffic|numa[5]           ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |traffic|numa[0]           ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |traffic|numb[5]           ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |traffic|numb[4]           ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |traffic|numb[0]           ;
; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |traffic|counta~6          ;
; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |traffic|countb~9          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Aug 15 23:45:03 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off traffic -c traffic
Info: Found 1 design units, including 1 entities, in source file traffic.v
    Info: Found entity 1: traffic
Info: Elaborating entity "traffic" for the top level hierarchy
Warning (10240): Verilog HDL Always Construct warning at traffic.v(21): inferring latch(es) for variable "ared", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "ared[7]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "ared[6]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "ared[5]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "ared[4]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "ared[3]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "ared[2]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "ared[1]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "ared[0]"
Warning (10240): Verilog HDL Always Construct warning at traffic.v(21): inferring latch(es) for variable "ayellow", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "ayellow[7]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "ayellow[6]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "ayellow[5]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "ayellow[4]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "ayellow[3]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "ayellow[2]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "ayellow[1]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "ayellow[0]"
Warning (10240): Verilog HDL Always Construct warning at traffic.v(21): inferring latch(es) for variable "agreen", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "agreen[7]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "agreen[6]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "agreen[5]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "agreen[4]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "agreen[3]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "agreen[2]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "agreen[1]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "agreen[0]"
Warning (10240): Verilog HDL Always Construct warning at traffic.v(21): inferring latch(es) for variable "aleft", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "aleft[7]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "aleft[6]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "aleft[5]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "aleft[4]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "aleft[3]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "aleft[2]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "aleft[1]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "aleft[0]"
Warning (10240): Verilog HDL Always Construct warning at traffic.v(21): inferring latch(es) for variable "bred", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bred[7]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bred[6]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bred[5]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bred[4]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bred[3]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bred[2]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bred[1]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bred[0]"
Warning (10240): Verilog HDL Always Construct warning at traffic.v(21): inferring latch(es) for variable "byellow", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "byellow[7]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "byellow[6]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "byellow[5]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "byellow[4]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "byellow[3]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "byellow[2]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "byellow[1]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "byellow[0]"
Warning (10240): Verilog HDL Always Construct warning at traffic.v(21): inferring latch(es) for variable "bleft", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bleft[7]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bleft[6]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bleft[5]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bleft[4]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bleft[3]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bleft[2]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bleft[1]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bleft[0]"
Warning (10240): Verilog HDL Always Construct warning at traffic.v(21): inferring latch(es) for variable "bgreen", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bgreen[7]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bgreen[6]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bgreen[5]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bgreen[4]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bgreen[3]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bgreen[2]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bgreen[1]"
Info (10041): Verilog HDL or VHDL info at traffic.v(18): inferred latch for "bgreen[0]"
Warning (10230): Verilog HDL assignment warning at traffic.v(62): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at traffic.v(64): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at traffic.v(99): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at traffic.v(102): truncated value with size 32 to match size of target (4)
Info: State machine "|traffic|counta" contains 5 states
Info: State machine "|traffic|countb" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|traffic|counta"
Info: Encoding result for state machine "|traffic|counta"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "counta.001"
        Info: Encoded state bit "counta.010"
        Info: Encoded state bit "counta.011"
        Info: Encoded state bit "counta.000"
        Info: Encoded state bit "counta.100"
    Info: State "|traffic|counta.000" uses code string "00000"
    Info: State "|traffic|counta.011" uses code string "00110"
    Info: State "|traffic|counta.010" uses code string "01010"
    Info: State "|traffic|counta.100" uses code string "00011"
    Info: State "|traffic|counta.001" uses code string "10010"
Info: Selected Auto state machine encoding method for state machine "|traffic|countb"
Info: Encoding result for state machine "|traffic|countb"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "countb.001"
        Info: Encoded state bit "countb.010"
        Info: Encoded state bit "countb.011"
        Info: Encoded state bit "countb.000"
        Info: Encoded state bit "countb.100"
    Info: State "|traffic|countb.000" uses code string "00000"
    Info: State "|traffic|countb.011" uses code string "00110"
    Info: State "|traffic|countb.010" uses code string "01010"
    Info: State "|traffic|countb.100" uses code string "00011"
    Info: State "|traffic|countb.001" uses code string "10010"
Info: Duplicate registers merged to single register
    Info: Duplicate register "counta.011" merged to single register "LAMPA[0]~reg0"
    Info: Duplicate register "counta.001" merged to single register "LAMPA[1]~reg0"
    Info: Duplicate register "counta.000" merged to single register "LAMPA[3]~reg0", power-up level changed
    Info: Duplicate register "countb.100" merged to single register "LAMPB[0]~reg0"
    Info: Duplicate register "countb.010" merged to single register "LAMPB[1]~reg0"
Info: Implemented 82 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 24 output pins
    Info: Implemented 56 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
    Info: Processing ended: Sat Aug 15 23:45:05 2009
    Info: Elapsed time: 00:00:02