mux.fit.eqn

一些Verilog学习程序B

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--A1L1 is Decoder~30 at LC97
A1L1_p1_out = b[1] & !b[2] & a & !b[0];
A1L1_p2_out = !a & c[1] & !c[2] & !c[0];
A1L1_or_out = A1L1_p1_out # A1L1_p2_out;
A1L1 = A1L1_or_out;


--A1L52 is reduce_or~510 at LC91
A1L52_p1_out = b[0] & a;
A1L52_p2_out = !a & c[0];
A1L52_p3_out = !a & !c[1] & c[2];
A1L52_p4_out = a & b[2] & !b[1];
A1L52_or_out = A1L52_p1_out # A1L52_p2_out # A1L52_p3_out # A1L52_p4_out;
A1L52 = A1L52_or_out;


--A1L62 is reduce_or~515 at LC85
A1L62_p1_out = c[2] & c[1] & !a & !c[0];
A1L62_p2_out = c[2] & !c[1] & !a & c[0];
A1L62_p3_out = a & b[2] & !b[1] & b[0];
A1L62_p4_out = a & b[2] & b[1] & !b[0];
A1L62_or_out = A1L62_p1_out # A1L62_p2_out # A1L62_p3_out # A1L62_p4_out;
A1L62 = A1L62_or_out;


--A1L72 is reduce_or~520 at LC88
A1L72_p1_out = c[2] & !c[0] & !c[1] & !a;
A1L72_p2_out = !c[2] & c[0] & !c[1] & !a;
A1L72_p3_out = a & !b[1] & !b[0] & b[2];
A1L72_p4_out = a & !b[1] & b[0] & !b[2];
A1L72_or_out = A1L72_p1_out # A1L72_p2_out # A1L72_p3_out # A1L72_p4_out;
A1L72 = A1L72_or_out;


--A1L82 is reduce_or~525 at LC99
A1L82_p1_out = !a & !c[2] & !c[1];
A1L82_p2_out = a & !b[2] & !b[1];
A1L82_p3_out = a & b[2] & b[1] & b[0];
A1L82_p4_out = !a & c[2] & c[1] & c[0];
A1L82_or_out = A1L82_p1_out # A1L82_p2_out # A1L82_p3_out # A1L82_p4_out;
A1L82 = A1L82_or_out;


--A1L92 is reduce_or~531 at LC93
A1L92_p0_out = b[0] & !b[1] & !b[2] & a;
A1L92_p1_out = b[0] & b[1] & b[2] & a;
A1L92_p2_out = !a & !c[1] & c[2] & !c[0];
A1L92_p3_out = !a & c[1] & c[2] & c[0];
A1L92_p4_out = !a & !c[1] & !c[2] & c[0];
A1L92_or_out = A1L73 # A1L92_p0_out # A1L92_p1_out # A1L92_p2_out # A1L92_p3_out # A1L92_p4_out;
A1L92 = A1L92_or_out;


--A1L03 is reduce_or~532 at SEXP85
A1L03 = EXP(!b[1] & !b[0] & a);


--A1L13 is reduce_or~533 at SEXP86
A1L13 = EXP(!b[1] & b[2] & a);


--A1L23 is reduce_or~534 at SEXP88
A1L23 = EXP(!b[0] & b[2] & a);


--A1L33 is reduce_or~535 at SEXP91
A1L33 = EXP(!c[1] & c[2] & !a);


--A1L43 is reduce_or~536 at SEXP92
A1L43 = EXP(!c[1] & !c[0] & !a);


--A1L53 is reduce_or~537 at SEXP94
A1L53 = EXP(c[2] & !c[0] & !a);


--A1L63 is reduce_or~538 at LC86
A1L63_p1_out = A1L03 & A1L13 & A1L23 & A1L33 & A1L43 & A1L53;
A1L63_or_out = A1L63_p1_out;
A1L63 = A1L63_or_out;


--A1L73 is reduce_or~540 at LC92
A1L73_p1_out = !b[0] & !b[1] & b[2] & a;
A1L73 = A1L73_p1_out;


--~VCC~0 is ~VCC~0 at LC94
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);


--~GND~0 is ~GND~0 at LC118
~GND~0_or_out = GND;
~GND~0 = ~GND~0_or_out;


--a is a at PIN_24
--operation mode is input

a = INPUT();


--b[0] is b[0] at PIN_22
--operation mode is input

b[0] = INPUT();


--b[1] is b[1] at PIN_21
--operation mode is input

b[1] = INPUT();


--b[2] is b[2] at PIN_20
--operation mode is input

b[2] = INPUT();


--c[0] is c[0] at PIN_18
--operation mode is input

c[0] = INPUT();


--c[1] is c[1] at PIN_17
--operation mode is input

c[1] = INPUT();


--c[2] is c[2] at PIN_16
--operation mode is input

c[2] = INPUT();


--d[0] is d[0] at PIN_61
--operation mode is output

d[0] = OUTPUT(~VCC~0);


--en is en at PIN_75
--operation mode is output

en = OUTPUT(~GND~0);


--d[5] is d[5] at PIN_63
--operation mode is output

d[5] = OUTPUT(A1L1);


--d[3] is d[3] at PIN_58
--operation mode is output

d[3] = OUTPUT(A1L52);


--d[6] is d[6] at PIN_55
--operation mode is output

d[6] = OUTPUT(A1L62);


--d[7] is d[7] at PIN_57
--operation mode is output

d[7] = OUTPUT(A1L72);


--d[1] is d[1] at PIN_64
--operation mode is output

d[1] = OUTPUT(A1L82);


--d[2] is d[2] at PIN_56
--operation mode is output

d[2] = OUTPUT(A1L63);


--d[4] is d[4] at PIN_60
--operation mode is output

d[4] = OUTPUT(A1L92);