mlt.hier_info

一些Verilog学习程序B

|mlt
a[0] => Mult0.IN1
a[1] => Mult0.IN0
b[0] => Mult0.IN3
b[1] => Mult0.IN2
c[0] <= <VCC>
c[1] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
c[2] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
c[3] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
c[4] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
c[5] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
c[6] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
c[7] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
en <= <GND>