mlt.fit.rpt

一些Verilog学习程序B

; Enable user-supplied start-up clock (CLKUSR) ; Off                 ;
; Enable device-wide reset (DEV_CLRn)          ; Off                 ;
; Enable device-wide output enable (DEV_OE)    ; Off                 ;
; Enable INIT_DONE output                      ; Off                 ;
; Configuration scheme                         ; Passive Serial      ;
; Reserve all unused pins                      ; As input tri-stated ;
; Base pin-out file on sameframe device        ; Off                 ;
+----------------------------------------------+---------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+----------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                  ;
+--------------------------------------------------------------------------------+-------+
; Name                                                                           ; Value ;
+--------------------------------------------------------------------------------+-------+
; Mid Wire Use - Fit Attempt 1                                                   ; 3     ;
; Mid Slack - Fit Attempt 1                                                      ; -8078 ;
; Internal Atom Count - Fit Attempt 1                                            ; 7     ;
; LE/ALM Count - Fit Attempt 1                                                   ; 7     ;
; LAB Count - Fit Attempt 1                                                      ; 1     ;
; Outputs per Lab - Fit Attempt 1                                                ; 7.000 ;
; Inputs per LAB - Fit Attempt 1                                                 ; 4.000 ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 0.000 ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:1   ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:1   ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:1   ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:1   ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:1   ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:1   ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:1   ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:1   ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:1   ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:1   ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:1   ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:1   ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:1   ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:1   ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 1:1   ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:1   ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:1   ;
; LEs in Chains - Fit Attempt 1                                                  ; 0     ;
; LEs in Long Chains - Fit Attempt 1                                             ; 0     ;
; LABs with Chains - Fit Attempt 1                                               ; 0     ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0     ;
; Time - Fit Attempt 1                                                           ; 0     ;
+--------------------------------------------------------------------------------+-------+


+---------------------------------------------+
; Advanced Data - Placement                   ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Early Wire Use - Fit Attempt 1      ; 1     ;
; Early Slack - Fit Attempt 1         ; -7858 ;
; Mid Wire Use - Fit Attempt 1        ; 2     ;
; Mid Slack - Fit Attempt 1           ; -7258 ;
; Late Wire Use - Fit Attempt 1       ; 2     ;
; Late Slack - Fit Attempt 1          ; -7258 ;
; Time - Fit Attempt 1                ; 0     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.234 ;
+-------------------------------------+-------+


+---------------------------------------------+
; Advanced Data - Routing                     ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Early Slack - Fit Attempt 1         ; -6979 ;
; Early Wire Use - Fit Attempt 1      ; 1     ;
; Peak Regional Wire - Fit Attempt 1  ; 1     ;
; Mid Slack - Fit Attempt 1           ; -7670 ;
; Late Slack - Fit Attempt 1          ; -7670 ;
; Late Slack - Fit Attempt 1          ; -7670 ;
; Late Wire Use - Fit Attempt 1       ; 1     ;
; Time - Fit Attempt 1                ; 0     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016 ;
+-------------------------------------+-------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Jan 11 21:07:19 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off mlt -c mlt
Info: Selected device EPM240T100C5 for design "mlt"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is pin to pin delay of 7.758 ns
    Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_29; Fanout = 7; PIN Node = 'b[0]'
    Info: 2: + IC(3.533 ns) + CELL(0.200 ns) = 4.865 ns; Loc. = LAB_X7_Y4; Fanout = 1; COMB Node = 'Decoder0~186'
    Info: 3: + IC(0.571 ns) + CELL(2.322 ns) = 7.758 ns; Loc. = PIN_78; Fanout = 0; PIN Node = 'c[5]'
    Info: Total cell delay = 3.654 ns ( 47.10 % )
    Info: Total interconnect delay = 4.104 ns ( 52.90 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 1%
    Info: The peak interconnect region extends from location x0_y0 to location x8_y5
Info: Fitter routing operations ending: elapsed time is 00:00:00
Warning: Following 2 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin c[0] has VCC driving its datain port
    Info: Pin en has GND driving its datain port
Info: Quartus II Fitter was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Jan 11 21:07:24 2009
    Info: Elapsed time: 00:00:06


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in E:/Verilog/基础实验/乘法器/mlt.fit.smsg.