mlt.fit.rpt

一些Verilog学习程序B

Fitter report for mlt
Sun Jan 11 21:07:24 2009
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. Input Pins
  7. Output Pins
  8. I/O Bank Usage
  9. All Package Pins
 10. Output Pin Default Load For Reported TCO
 11. Fitter Resource Utilization by Entity
 12. Delay Chain Summary
 13. Non-Global High Fan-Out Signals
 14. Interconnect Usage Summary
 15. LAB Logic Elements
 16. LAB Signals Sourced
 17. LAB Signals Sourced Out
 18. LAB Distinct Inputs
 19. Fitter Device Options
 20. Advanced Data - General
 21. Advanced Data - Placement Preparation
 22. Advanced Data - Placement
 23. Advanced Data - Routing
 24. Fitter Messages
 25. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------+
; Fitter Summary                                                   ;
+-----------------------+------------------------------------------+
; Fitter Status         ; Successful - Sun Jan 11 21:07:24 2009    ;
; Quartus II Version    ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name         ; mlt                                      ;
; Top-level Entity Name ; mlt                                      ;
; Family                ; MAX II                                   ;
; Device                ; EPM240T100C5                             ;
; Timing Models         ; Final                                    ;
; Total logic elements  ; 7 / 240 ( 3 % )                          ;
; Total pins            ; 13 / 80 ( 16 % )                         ;
; Total virtual pins    ; 0                                        ;
; UFM blocks            ; 0 / 1 ( 0 % )                            ;
+-----------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                              ;
+--------------------------------------------------------+--------------------+--------------------------------+
; Option                                                 ; Setting            ; Default Value                  ;
+--------------------------------------------------------+--------------------+--------------------------------+
; Device                                                 ; EPM240T100C5       ;                                ;
; Optimize Hold Timing                                   ; Off                ; IO Paths and Minimum TPD Paths ;
; Fitter Effort                                          ; Standard Fit       ; Auto Fit                       ;
; Use smart compilation                                  ; Off                ; Off                            ;
; Router Timing Optimization Level                       ; Normal             ; Normal                         ;
; Placement Effort Multiplier                            ; 1.0                ; 1.0                            ;
; Router Effort Multiplier                               ; 1.0                ; 1.0                            ;
; Optimize Fast-Corner Timing                            ; Off                ; Off                            ;
; Guarantee I/O Paths Have Zero Hold Time at Fast Corner ; On                 ; On                             ;
; PowerPlay Power Optimization                           ; Normal compilation ; Normal compilation             ;
; Optimize Timing                                        ; Normal compilation ; Normal compilation             ;
; Optimize IOC Register Placement for Timing             ; On                 ; On                             ;
; Limit to One Fitting Attempt                           ; Off                ; Off                            ;
; Final Placement Optimizations                          ; Automatically      ; Automatically                  ;
; Fitter Aggressive Routability Optimizations            ; Automatically      ; Automatically                  ;
; Fitter Initial Placement Seed                          ; 1                  ; 1                              ;
; Slow Slew Rate                                         ; Off                ; Off                            ;
; PCI I/O                                                ; Off                ; Off                            ;
; Weak Pull-Up Resistor                                  ; Off                ; Off                            ;
; Enable Bus-Hold Circuitry                              ; Off                ; Off                            ;
; Auto Delay Chains                                      ; On                 ; On                             ;
; Perform Physical Synthesis for Combinational Logic     ; Off                ; Off                            ;
; Perform Register Duplication                           ; Off                ; Off                            ;
; Perform Register Retiming                              ; Off                ; Off                            ;
; Perform Asynchronous Signal Pipelining                 ; Off                ; Off                            ;
; Physical Synthesis Effort Level                        ; Normal             ; Normal                         ;
; Logic Cell Insertion - Logic Duplication               ; Auto               ; Auto                           ;
; Auto Register Duplication                              ; Auto               ; Auto                           ;
; Auto Global Clock                                      ; On                 ; On                             ;
; Auto Global Register Control Signals                   ; On                 ; On                             ;
; Always Enable Input Buffers                            ; Off                ; Off                            ;
+--------------------------------------------------------+--------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/Verilog/基础实验/乘法器/mlt.pin.


+----------------------------------------------------------------+
; Fitter Resource Usage Summary                                  ;
+---------------------------------------------+------------------+
; Resource                                    ; Usage            ;
+---------------------------------------------+------------------+
; Total logic elements                        ; 7 / 240 ( 3 % )  ;
;     -- Combinational with no register       ; 7                ;
;     -- Register only                        ; 0                ;
;     -- Combinational with a register        ; 0                ;
;                                             ;                  ;
; Logic element usage by number of LUT inputs ;                  ;
;     -- 4 input functions                    ; 7                ;
;     -- 3 input functions                    ; 0                ;
;     -- 2 input functions                    ; 0                ;
;     -- 1 input functions                    ; 0                ;
;     -- 0 input functions                    ; 0                ;
;                                             ;                  ;
; Logic elements by mode                      ;                  ;
;     -- normal mode                          ; 7                ;
;     -- arithmetic mode                      ; 0                ;
;     -- qfbk mode                            ; 0                ;
;     -- register cascade mode                ; 0                ;
;     -- synchronous clear/load mode          ; 0                ;
;     -- asynchronous clear/load mode         ; 0                ;
;                                             ;                  ;
; Total LABs                                  ; 2 / 24 ( 8 % )   ;
; Logic elements in carry chains              ; 0                ;
; User inserted logic elements                ; 0                ;
; Virtual pins                                ; 0                ;
; I/O pins                                    ; 13 / 80 ( 16 % ) ;
;     -- Clock pins                           ; 0 / 0 ( -- )     ;
; Global signals                              ; 0                ;
; UFM blocks                                  ; 0 / 1 ( 0 % )    ;