📄 mlt.tan.rpt
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Timing Analyzer report for mlt
Sun Jan 11 21:07:33 2009
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 8.265 ns ; b[1] ; c[7] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM240T100C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 8.265 ns ; b[1] ; c[7] ;
; N/A ; None ; 8.243 ns ; b[1] ; c[6] ;
; N/A ; None ; 8.233 ns ; b[1] ; c[5] ;
; N/A ; None ; 8.019 ns ; b[0] ; c[7] ;
; N/A ; None ; 7.999 ns ; b[0] ; c[6] ;
; N/A ; None ; 7.993 ns ; b[0] ; c[5] ;
; N/A ; None ; 7.893 ns ; a[0] ; c[7] ;
; N/A ; None ; 7.870 ns ; a[0] ; c[6] ;
; N/A ; None ; 7.860 ns ; a[0] ; c[5] ;
; N/A ; None ; 7.811 ns ; a[0] ; c[2] ;
; N/A ; None ; 7.808 ns ; a[0] ; c[4] ;
; N/A ; None ; 7.807 ns ; a[0] ; c[3] ;
; N/A ; None ; 7.807 ns ; a[0] ; c[1] ;
; N/A ; None ; 7.692 ns ; b[1] ; c[1] ;
; N/A ; None ; 7.691 ns ; b[1] ; c[2] ;
; N/A ; None ; 7.684 ns ; b[1] ; c[3] ;
; N/A ; None ; 7.682 ns ; b[1] ; c[4] ;
; N/A ; None ; 7.653 ns ; a[1] ; c[2] ;
; N/A ; None ; 7.653 ns ; a[1] ; c[1] ;
; N/A ; None ; 7.646 ns ; a[1] ; c[7] ;
; N/A ; None ; 7.645 ns ; a[1] ; c[3] ;
; N/A ; None ; 7.644 ns ; a[1] ; c[4] ;
; N/A ; None ; 7.626 ns ; a[1] ; c[6] ;
; N/A ; None ; 7.620 ns ; a[1] ; c[5] ;
; N/A ; None ; 7.427 ns ; b[0] ; c[2] ;
; N/A ; None ; 7.427 ns ; b[0] ; c[1] ;
; N/A ; None ; 7.421 ns ; b[0] ; c[4] ;
; N/A ; None ; 7.420 ns ; b[0] ; c[3] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Sun Jan 11 21:07:32 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mlt -c mlt
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Longest tpd from source pin "b[1]" to destination pin "c[7]" is 8.265 ns
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_30; Fanout = 7; PIN Node = 'b[1]'
Info: 2: + IC(3.257 ns) + CELL(0.914 ns) = 5.303 ns; Loc. = LC_X7_Y4_N2; Fanout = 1; COMB Node = 'WideOr0~4'
Info: 3: + IC(0.640 ns) + CELL(2.322 ns) = 8.265 ns; Loc. = PIN_76; Fanout = 0; PIN Node = 'c[7]'
Info: Total cell delay = 4.368 ns ( 52.85 % )
Info: Total interconnect delay = 3.897 ns ( 47.15 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Sun Jan 11 21:07:33 2009
Info: Elapsed time: 00:00:02
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