div.hier_info

一些Verilog学习程序B

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a[0] => LessThan2.IN3
a[1] => LessThan1.IN3
a[1] => Add1.IN6
a[1] => temp_reg~2.DATAA
a[2] => LessThan0.IN3
a[2] => Add0.IN6
a[2] => temp_reg~0.DATAA
b[0] => LessThan0.IN6
b[0] => LessThan1.IN6
b[0] => LessThan2.IN6
b[0] => Equal0.IN31
b[0] => Add0.IN5
b[0] => Add1.IN4
b[1] => LessThan0.IN5
b[1] => LessThan1.IN5
b[1] => LessThan2.IN5
b[1] => Equal0.IN30
b[1] => Add0.IN4
b[1] => Add1.IN3
b[2] => LessThan0.IN4
b[2] => LessThan1.IN4
b[2] => LessThan2.IN4
b[2] => Equal0.IN29
b[2] => Add0.IN3
b[2] => Add1.IN2
c[0] <= <VCC>
c[1] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
c[2] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
c[3] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
c[4] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
c[5] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
c[6] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
c[7] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
en[0] <= <GND>
en[1] <= <GND>
en[2] <= <GND>
en[3] <= <GND>
en[4] <= <GND>
en[5] <= <GND>
en[6] <= <GND>
en[7] <= <GND>