div.tan.qmsg

一些Verilog学习程序B

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jan 11 21:13:09 2009 " "Info: Processing started: Sun Jan 11 21:13:09 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off div -c div " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off div -c div" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[2\] c\[3\] 11.385 ns Longest " "Info: Longest tpd from source pin \"a\[2\]\" to destination pin \"c\[3\]\" is 11.385 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns a\[2\] 1 PIN PIN_29 10 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_29; Fanout = 10; PIN Node = 'a\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { a[2] } "NODE_NAME" } } { "div.v" "" { Text "E:/Verilog/基础实验/除法器/div.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.189 ns) + CELL(0.511 ns) 3.832 ns LessThan1~100 2 COMB LC_X2_Y1_N4 1 " "Info: 2: + IC(2.189 ns) + CELL(0.511 ns) = 3.832 ns; Loc. = LC_X2_Y1_N4; Fanout = 1; COMB Node = 'LessThan1~100'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.700 ns" { a[2] LessThan1~100 } "NODE_NAME" } } { "div.v" "" { Text "E:/Verilog/基础实验/除法器/div.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.135 ns) + CELL(0.200 ns) 5.167 ns LessThan1~101 3 COMB LC_X3_Y1_N5 4 " "Info: 3: + IC(1.135 ns) + CELL(0.200 ns) = 5.167 ns; Loc. = LC_X3_Y1_N5; Fanout = 4; COMB Node = 'LessThan1~101'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.335 ns" { LessThan1~100 LessThan1~101 } "NODE_NAME" } } { "div.v" "" { Text "E:/Verilog/基础实验/除法器/div.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.821 ns) + CELL(0.511 ns) 6.499 ns WideOr4~4 4 COMB LC_X3_Y1_N4 1 " "Info: 4: + IC(0.821 ns) + CELL(0.511 ns) = 6.499 ns; Loc. = LC_X3_Y1_N4; Fanout = 1; COMB Node = 'WideOr4~4'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.332 ns" { LessThan1~101 WideOr4~4 } "NODE_NAME" } } { "div.v" "" { Text "E:/Verilog/基础实验/除法器/div.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.564 ns) + CELL(2.322 ns) 11.385 ns c\[3\] 5 PIN PIN_82 0 " "Info: 5: + IC(2.564 ns) + CELL(2.322 ns) = 11.385 ns; Loc. = PIN_82; Fanout = 0; PIN Node = 'c\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.886 ns" { WideOr4~4 c[3] } "NODE_NAME" } } { "div.v" "" { Text "E:/Verilog/基础实验/除法器/div.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.676 ns ( 41.07 % ) " "Info: Total cell delay = 4.676 ns ( 41.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.709 ns ( 58.93 % ) " "Info: Total interconnect delay = 6.709 ns ( 58.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.385 ns" { a[2] LessThan1~100 LessThan1~101 WideOr4~4 c[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.385 ns" { a[2] a[2]~combout LessThan1~100 LessThan1~101 WideOr4~4 c[3] } { 0.000ns 0.000ns 2.189ns 1.135ns 0.821ns 2.564ns } { 0.000ns 1.132ns 0.511ns 0.200ns 0.511ns 2.322ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 11 21:13:10 2009 " "Info: Processing ended: Sun Jan 11 21:13:10 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}