📄 div.tan.rpt
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Timing Analyzer report for div
Sun Jan 11 21:13:10 2009
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 11.385 ns ; a[2] ; c[3] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM240T100C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 11.385 ns ; a[2] ; c[3] ;
; N/A ; None ; 11.381 ns ; a[2] ; c[7] ;
; N/A ; None ; 11.374 ns ; a[2] ; c[4] ;
; N/A ; None ; 11.344 ns ; a[2] ; c[2] ;
; N/A ; None ; 11.319 ns ; b[1] ; c[7] ;
; N/A ; None ; 11.315 ns ; b[1] ; c[3] ;
; N/A ; None ; 11.274 ns ; b[1] ; c[2] ;
; N/A ; None ; 11.210 ns ; a[1] ; c[7] ;
; N/A ; None ; 11.206 ns ; a[1] ; c[3] ;
; N/A ; None ; 11.165 ns ; a[1] ; c[2] ;
; N/A ; None ; 11.087 ns ; b[0] ; c[7] ;
; N/A ; None ; 11.084 ns ; b[0] ; c[3] ;
; N/A ; None ; 11.073 ns ; b[0] ; c[4] ;
; N/A ; None ; 11.067 ns ; b[1] ; c[4] ;
; N/A ; None ; 11.044 ns ; b[0] ; c[2] ;
; N/A ; None ; 10.967 ns ; a[2] ; c[5] ;
; N/A ; None ; 10.912 ns ; b[2] ; c[7] ;
; N/A ; None ; 10.908 ns ; b[2] ; c[3] ;
; N/A ; None ; 10.867 ns ; b[2] ; c[2] ;
; N/A ; None ; 10.810 ns ; b[0] ; c[5] ;
; N/A ; None ; 10.793 ns ; b[1] ; c[5] ;
; N/A ; None ; 10.785 ns ; a[1] ; c[4] ;
; N/A ; None ; 10.619 ns ; b[2] ; c[4] ;
; N/A ; None ; 10.450 ns ; a[0] ; c[7] ;
; N/A ; None ; 10.446 ns ; a[0] ; c[3] ;
; N/A ; None ; 10.437 ns ; a[1] ; c[5] ;
; N/A ; None ; 10.405 ns ; a[0] ; c[2] ;
; N/A ; None ; 10.313 ns ; a[2] ; c[1] ;
; N/A ; None ; 10.155 ns ; b[0] ; c[1] ;
; N/A ; None ; 10.137 ns ; b[1] ; c[1] ;
; N/A ; None ; 9.983 ns ; a[0] ; c[4] ;
; N/A ; None ; 9.783 ns ; a[1] ; c[1] ;
; N/A ; None ; 9.767 ns ; b[2] ; c[5] ;
; N/A ; None ; 9.582 ns ; a[0] ; c[5] ;
; N/A ; None ; 9.261 ns ; a[2] ; c[6] ;
; N/A ; None ; 9.182 ns ; a[1] ; c[6] ;
; N/A ; None ; 9.122 ns ; a[0] ; c[6] ;
; N/A ; None ; 9.113 ns ; b[2] ; c[1] ;
; N/A ; None ; 8.995 ns ; b[1] ; c[6] ;
; N/A ; None ; 8.931 ns ; a[0] ; c[1] ;
; N/A ; None ; 8.765 ns ; b[2] ; c[6] ;
; N/A ; None ; 8.684 ns ; b[0] ; c[6] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Sun Jan 11 21:13:09 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off div -c div
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Longest tpd from source pin "a[2]" to destination pin "c[3]" is 11.385 ns
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_29; Fanout = 10; PIN Node = 'a[2]'
Info: 2: + IC(2.189 ns) + CELL(0.511 ns) = 3.832 ns; Loc. = LC_X2_Y1_N4; Fanout = 1; COMB Node = 'LessThan1~100'
Info: 3: + IC(1.135 ns) + CELL(0.200 ns) = 5.167 ns; Loc. = LC_X3_Y1_N5; Fanout = 4; COMB Node = 'LessThan1~101'
Info: 4: + IC(0.821 ns) + CELL(0.511 ns) = 6.499 ns; Loc. = LC_X3_Y1_N4; Fanout = 1; COMB Node = 'WideOr4~4'
Info: 5: + IC(2.564 ns) + CELL(2.322 ns) = 11.385 ns; Loc. = PIN_82; Fanout = 0; PIN Node = 'c[3]'
Info: Total cell delay = 4.676 ns ( 41.07 % )
Info: Total interconnect delay = 6.709 ns ( 58.93 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Sun Jan 11 21:13:10 2009
Info: Elapsed time: 00:00:02
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