div.fit.eqn

一些Verilog学习程序B

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--A1L13 is reduce_or~1016 at LC91
A1L13_p0_out = a[2] & !b[2] & !a[1] & b[0];
A1L13_p1_out = a[2] & !b[1] & b[2] & a[1];
A1L13_p2_out = a[2] & b[1] & a[1] & !b[0];
A1L13_p3_out = a[2] & b[2] & a[1] & a[0];
A1L13_p4_out = b[1] & !b[2] & a[1] & !b[0];
A1L13_or_out = A1L24 # A1L13_p0_out # A1L13_p1_out # A1L13_p2_out # A1L13_p3_out # A1L13_p4_out;
A1L13 = A1L13_or_out;


--A1L23 is reduce_or~1020 at LC85
A1L23_p1_out = !b[0] & !b[2] & !b[1];
A1L23_p2_out = !b[2] & !b[1] & a[2] & !a[1] & a[0];
A1L23_p3_out = !b[2] & !b[1] & a[2] & a[1] & !a[0];
A1L23_or_out = A1L23_p1_out # A1L23_p2_out # A1L23_p3_out;
A1L23 = A1L23_or_out;


--A1L33 is reduce_or~1026 at LC88
A1L33_p0_out = !a[2] & b[1] & a[1] & !b[0] & !b[2];
A1L33_p1_out = a[0] & !a[2] & !b[1] & !a[1] & b[0] & !b[2];
A1L33_p2_out = a[2] & b[1] & !a[1] & b[0] & !b[2];
A1L33_p3_out = !a[0] & a[2] & !a[1] & b[0] & !b[2];
A1L33_p4_out = a[0] & !a[2] & b[1] & a[1] & !b[2];
A1L33_or_out = A1L34 # A1L33_p0_out # A1L33_p1_out # A1L33_p2_out # A1L33_p3_out # A1L33_p4_out;
A1L33 = A1L33_or_out;


--A1L43 is reduce_or~1031 at LC99
A1L43_p1_out = !a[2] & !a[1] & b[0];
A1L43_p2_out = !a[1] & b[0] & b[1];
A1L43_p3_out = !a[2] & b[1];
A1L43_p4_out = a[2] & a[1] & b[0] & !b[1] & a[0];
A1L43_or_out = b[2] # A1L43_p1_out # A1L43_p2_out # A1L43_p3_out # A1L43_p4_out;
A1L43 = A1L43_or_out;


--A1L53 is reduce_or~1033 at LC93
A1L53_p0_out = !a[1] & b[2] & b[1];
A1L53_p2_out = a[2] & !a[1] & b[0] & !a[0];
A1L53_p3_out = !a[2] & b[2];
A1L53_p4_out = b[0] & !a[0] & b[2] & b[1];
A1L53_or_out = A1L44 # A1L53_p0_out # A1L53_p2_out # A1L53_p3_out # A1L53_p4_out;
A1L53 = b[2] $ A1L53_or_out;


--A1L63 is reduce_or~1044 at LC97
A1L63_p1_out = !b[2] & !a[1] & !b[0] & a[2];
A1L63_p2_out = !b[2] & !b[0] & !b[1];
A1L63_p3_out = !b[2] & a[1] & b[0] & a[2] & b[1];
A1L63_p4_out = !b[2] & a[1] & !a[2] & !b[1] & !a[0];
A1L63_or_out = A1L63_p1_out # A1L63_p2_out # A1L63_p3_out # A1L63_p4_out;
A1L63 = A1L63_or_out;


--A1L73 is reduce_or~1045 at SEXP81
A1L73 = EXP(a[1] & a[0]);


--A1L83 is reduce_or~1046 at SEXP94
A1L83 = EXP(!b[2] & a[2]);


--A1L93 is reduce_or~1047 at SEXP90
A1L93 = EXP(!b[2] & !b[0] & !b[1]);


--A1L04 is reduce_or~1048 at SEXP85
A1L04 = EXP(b[0] & !b[1] & !a[1] & !a[0]);


--A1L14 is reduce_or~1053 at LC86
A1L14_p1_out = A1L93 & A1L04;
A1L14_p0_out = A1L93 & A1L04 & b[1] & A1L83 & b[0] & !a[0];
A1L14_p2_out = A1L93 & A1L04 & b[2] & !a[2];
A1L14_p3_out = A1L93 & A1L04 & !b[2] & a[2] & A1L73 & !b[1];
A1L14_p4_out = A1L93 & A1L04 & b[1] & A1L83 & !a[1];
A1L14_or_out = A1L14_p0_out # A1L14_p2_out # A1L14_p3_out # A1L14_p4_out;
A1L14 = A1L14_p1_out $ A1L14_or_out;


--A1L24 is reduce_or~1056 at LC90
A1L24_p1_out = a[0] & a[2] & !b[1] & b[0];
A1L24_p2_out = a[0] & !b[1] & b[0] & !b[2];
A1L24_p3_out = a[0] & !a[2] & b[0] & !b[2] & a[1];
A1L24_p4_out = a[2] & !b[1] & !b[0] & b[2];
A1L24 = A1L24_p1_out # A1L24_p2_out # A1L24_p3_out # A1L24_p4_out;


--A1L34 is reduce_or~1061 at LC87
A1L34_p0_out = a[2] & a[1] & b[2] & a[0];
A1L34_p1_out = a[2] & !b[1] & a[1] & b[2];
A1L34_p2_out = a[2] & !b[1] & b[2] & a[0];
A1L34_p3_out = a[2] & !b[1] & b[2] & !b[0];
A1L34_p4_out = a[2] & a[1] & b[2] & !b[0];
A1L34 = A1L34_p0_out # A1L34_p1_out # A1L34_p2_out # A1L34_p3_out # A1L34_p4_out;


--A1L44 is reduce_or~1067 at LC92
A1L44_p0_out = !a[2] & b[1] & a[1] & a[0];
A1L44_p1_out = a[2] & !b[1] & !b[2] & a[1] & b[0] & a[0];
A1L44_p2_out = !a[2] & !b[1] & !a[1] & b[0] & a[0];
A1L44_p3_out = !a[2] & b[1] & a[1] & !b[0];
A1L44_p4_out = a[2] & b[1] & !a[1] & b[0];
A1L44 = A1L44_p0_out # A1L44_p1_out # A1L44_p2_out # A1L44_p3_out # A1L44_p4_out;


--~VCC~0 is ~VCC~0 at LC94
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);


--~GND~0 is ~GND~0 at LC118
~GND~0_or_out = GND;
~GND~0 = ~GND~0_or_out;


--~GND~1 is ~GND~1 at LC117
~GND~1_or_out = GND;
~GND~1 = ~GND~1_or_out;


--~GND~2 is ~GND~2 at LC115
~GND~2_or_out = GND;
~GND~2 = ~GND~2_or_out;


--~GND~3 is ~GND~3 at LC109
~GND~3_or_out = GND;
~GND~3 = ~GND~3_or_out;


--~GND~4 is ~GND~4 at LC107
~GND~4_or_out = GND;
~GND~4 = ~GND~4_or_out;


--~GND~5 is ~GND~5 at LC105
~GND~5_or_out = GND;
~GND~5 = ~GND~5_or_out;


--~GND~6 is ~GND~6 at LC104
~GND~6_or_out = GND;
~GND~6 = ~GND~6_or_out;


--~GND~7 is ~GND~7 at LC101
~GND~7_or_out = GND;
~GND~7 = ~GND~7_or_out;


--a[0] is a[0] at PIN_24
--operation mode is input

a[0] = INPUT();


--a[1] is a[1] at PIN_22
--operation mode is input

a[1] = INPUT();


--a[2] is a[2] at PIN_21
--operation mode is input

a[2] = INPUT();


--b[0] is b[0] at PIN_20
--operation mode is input

b[0] = INPUT();


--b[1] is b[1] at PIN_18
--operation mode is input

b[1] = INPUT();


--b[2] is b[2] at PIN_17
--operation mode is input

b[2] = INPUT();


--c[0] is c[0] at PIN_61
--operation mode is output

c[0] = OUTPUT(~VCC~0);


--en[0] is en[0] at PIN_75
--operation mode is output

en[0] = OUTPUT(~GND~0);


--en[1] is en[1] at PIN_74
--operation mode is output

en[1] = OUTPUT(~GND~1);


--en[2] is en[2] at PIN_73
--operation mode is output

en[2] = OUTPUT(~GND~2);


--en[3] is en[3] at PIN_70
--operation mode is output

en[3] = OUTPUT(~GND~3);


--en[4] is en[4] at PIN_69
--operation mode is output

en[4] = OUTPUT(~GND~4);


--en[5] is en[5] at PIN_68
--operation mode is output

en[5] = OUTPUT(~GND~5);


--en[6] is en[6] at PIN_67
--operation mode is output

en[6] = OUTPUT(~GND~6);


--en[7] is en[7] at PIN_65
--operation mode is output

en[7] = OUTPUT(~GND~7);


--c[3] is c[3] at PIN_58
--operation mode is output

c[3] = OUTPUT(A1L13);


--c[6] is c[6] at PIN_55
--operation mode is output

c[6] = OUTPUT(A1L23);


--c[7] is c[7] at PIN_57
--operation mode is output

c[7] = OUTPUT(A1L33);


--c[1] is c[1] at PIN_64
--operation mode is output

c[1] = OUTPUT(A1L43);


--c[2] is c[2] at PIN_56
--operation mode is output

c[2] = OUTPUT(A1L14);


--c[4] is c[4] at PIN_60
--operation mode is output

c[4] = OUTPUT(A1L53);


--c[5] is c[5] at PIN_63
--operation mode is output

c[5] = OUTPUT(A1L63);