cmp.tan.qmsg

一些Verilog学习程序B

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jan 11 21:45:06 2009 " "Info: Processing started: Sun Jan 11 21:45:06 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off cmp -c cmp " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cmp -c cmp" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "b\[1\] c\[7\] 10.000 ns Longest " "Info: Longest tpd from source pin \"b\[1\]\" to destination pin \"c\[7\]\" is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns b\[1\] 1 PIN PIN_34 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_34; Fanout = 1; PIN Node = 'b\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { b[1] } "NODE_NAME" } } { "cmp.v" "" { Text "E:/Verilog/基础实验/四位比较器/cmp.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.070 ns) + CELL(0.914 ns) 4.116 ns LessThan0~348 2 COMB LC_X3_Y1_N1 1 " "Info: 2: + IC(2.070 ns) + CELL(0.914 ns) = 4.116 ns; Loc. = LC_X3_Y1_N1; Fanout = 1; COMB Node = 'LessThan0~348'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.984 ns" { b[1] LessThan0~348 } "NODE_NAME" } } { "cmp.v" "" { Text "E:/Verilog/基础实验/四位比较器/cmp.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 4.621 ns LessThan0~349 3 COMB LC_X3_Y1_N2 1 " "Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 4.621 ns; Loc. = LC_X3_Y1_N2; Fanout = 1; COMB Node = 'LessThan0~349'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.505 ns" { LessThan0~348 LessThan0~349 } "NODE_NAME" } } { "cmp.v" "" { Text "E:/Verilog/基础实验/四位比较器/cmp.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 5.126 ns LessThan0~350 4 COMB LC_X3_Y1_N3 4 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 5.126 ns; Loc. = LC_X3_Y1_N3; Fanout = 4; COMB Node = 'LessThan0~350'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.505 ns" { LessThan0~349 LessThan0~350 } "NODE_NAME" } } { "cmp.v" "" { Text "E:/Verilog/基础实验/四位比较器/cmp.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.552 ns) + CELL(2.322 ns) 10.000 ns c\[7\] 5 PIN PIN_76 0 " "Info: 5: + IC(2.552 ns) + CELL(2.322 ns) = 10.000 ns; Loc. = PIN_76; Fanout = 0; PIN Node = 'c\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.874 ns" { LessThan0~350 c[7] } "NODE_NAME" } } { "cmp.v" "" { Text "E:/Verilog/基础实验/四位比较器/cmp.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.768 ns ( 47.68 % ) " "Info: Total cell delay = 4.768 ns ( 47.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.232 ns ( 52.32 % ) " "Info: Total interconnect delay = 5.232 ns ( 52.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { b[1] LessThan0~348 LessThan0~349 LessThan0~350 c[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { b[1] b[1]~combout LessThan0~348 LessThan0~349 LessThan0~350 c[7] } { 0.000ns 0.000ns 2.070ns 0.305ns 0.305ns 2.552ns } { 0.000ns 1.132ns 0.914ns 0.200ns 0.200ns 2.322ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 11 21:45:07 2009 " "Info: Processing ended: Sun Jan 11 21:45:07 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}