clock.map.qmsg

一些Verilog学习程序B

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jun 06 22:50:13 2009 " "Info: Processing started: Sat Jun 06 22:50:13 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clock.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock " "Info: Elaborating entity \"clock\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(18) " "Warning (10230): Verilog HDL assignment warning at clock.v(18): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 18 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(19) " "Warning (10230): Verilog HDL assignment warning at clock.v(19): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 19 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(20) " "Warning (10230): Verilog HDL assignment warning at clock.v(20): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 20 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(21) " "Warning (10230): Verilog HDL assignment warning at clock.v(21): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 21 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(22) " "Warning (10230): Verilog HDL assignment warning at clock.v(22): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 22 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(23) " "Warning (10230): Verilog HDL assignment warning at clock.v(23): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 23 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 clock.v(32) " "Warning (10230): Verilog HDL assignment warning at clock.v(32): truncated value with size 32 to match size of target (16)" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 32 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 26 clock.v(69) " "Warning (10230): Verilog HDL assignment warning at clock.v(69): truncated value with size 32 to match size of target (26)" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 69 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(89) " "Warning (10230): Verilog HDL assignment warning at clock.v(89): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 89 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(93) " "Warning (10230): Verilog HDL assignment warning at clock.v(93): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 93 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(97) " "Warning (10230): Verilog HDL assignment warning at clock.v(97): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 97 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(101) " "Warning (10230): Verilog HDL assignment warning at clock.v(101): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 101 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(105) " "Warning (10230): Verilog HDL assignment warning at clock.v(105): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 105 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(109) " "Warning (10230): Verilog HDL assignment warning at clock.v(109): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 109 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "dataout_buf\[5\]\[3\] clock.v(12) " "Info (10041): Verilog HDL or VHDL info at clock.v(12): inferred latch for \"dataout_buf\[5\]\[3\]\"" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "dataout_buf\[5\]\[2\] clock.v(12) " "Info (10041): Verilog HDL or VHDL info at clock.v(12): inferred latch for \"dataout_buf\[5\]\[2\]\"" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "dataout_buf\[5\]\[1\] clock.v(12) " "Info (10041): Verilog HDL or VHDL info at clock.v(12): inferred latch for \"dataout_buf\[5\]\[1\]\"" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "dataout_buf\[5\]\[0\] clock.v(12) " "Info (10041): Verilog HDL or VHDL info at clock.v(12): inferred latch for \"dataout_buf\[5\]\[0\]\"" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "dataout_buf\[2\]\[3\] clock.v(12) " "Info (10041): Verilog HDL or VHDL info at clock.v(12): inferred latch for \"dataout_buf\[2\]\[3\]\"" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "dataout_buf\[2\]\[2\] clock.v(12) " "Info (10041): Verilog HDL or VHDL info at clock.v(12): inferred latch for \"dataout_buf\[2\]\[2\]\"" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}