clock.tan.qmsg

一些Verilog学习程序B

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dataout\[3\]\$latch " "Info: Node \"dataout\[3\]\$latch\"" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dataout\[2\]\$latch " "Info: Node \"dataout\[2\]\$latch\"" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dataout\[1\]\$latch " "Info: Node \"dataout\[1\]\$latch\"" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dataout\[0\]\$latch " "Info: Node \"dataout\[0\]\$latch\"" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 6 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[6\] register dataout_buf\[4\]\[0\] 102.3 MHz 9.775 ns Internal " "Info: Clock \"clk\" has Internal fmax of 102.3 MHz between source register \"cnt\[6\]\" and destination register \"dataout_buf\[4\]\[0\]\" (period= 9.775 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.066 ns + Longest register register " "Info: + Longest register to register delay is 9.066 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[6\] 1 REG LC_X3_Y2_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y2_N1; Fanout = 4; REG Node = 'cnt\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cnt[6] } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.288 ns) + CELL(0.914 ns) 2.202 ns Equal9~290 2 COMB LC_X4_Y2_N0 1 " "Info: 2: + IC(1.288 ns) + CELL(0.914 ns) = 2.202 ns; Loc. = LC_X4_Y2_N0; Fanout = 1; COMB Node = 'Equal9~290'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.202 ns" { cnt[6] Equal9~290 } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.740 ns) 3.672 ns Equal9~292 3 COMB LC_X4_Y2_N4 1 " "Info: 3: + IC(0.730 ns) + CELL(0.740 ns) = 3.672 ns; Loc. = LC_X4_Y2_N4; Fanout = 1; COMB Node = 'Equal9~292'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.470 ns" { Equal9~290 Equal9~292 } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.767 ns) + CELL(0.511 ns) 4.950 ns Equal9~293 4 COMB LC_X4_Y2_N1 20 " "Info: 4: + IC(0.767 ns) + CELL(0.511 ns) = 4.950 ns; Loc. = LC_X4_Y2_N1; Fanout = 20; COMB Node = 'Equal9~293'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.278 ns" { Equal9~292 Equal9~293 } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.991 ns) + CELL(0.200 ns) 7.141 ns dataout_buf\[4\]\[3\]~1502 5 COMB LC_X5_Y3_N7 4 " "Info: 5: + IC(1.991 ns) + CELL(0.200 ns) = 7.141 ns; Loc. = LC_X5_Y3_N7; Fanout = 4; COMB Node = 'dataout_buf\[4\]\[3\]~1502'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.191 ns" { Equal9~293 dataout_buf[4][3]~1502 } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.682 ns) + CELL(1.243 ns) 9.066 ns dataout_buf\[4\]\[0\] 6 REG LC_X5_Y3_N4 5 " "Info: 6: + IC(0.682 ns) + CELL(1.243 ns) = 9.066 ns; Loc. = LC_X5_Y3_N4; Fanout = 5; REG Node = 'dataout_buf\[4\]\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.925 ns" { dataout_buf[4][3]~1502 dataout_buf[4][0] } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.608 ns ( 39.80 % ) " "Info: Total cell delay = 3.608 ns ( 39.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.458 ns ( 60.20 % ) " "Info: Total interconnect delay = 5.458 ns ( 60.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.066 ns" { cnt[6] Equal9~290 Equal9~292 Equal9~293 dataout_buf[4][3]~1502 dataout_buf[4][0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.066 ns" { cnt[6] Equal9~290 Equal9~292 Equal9~293 dataout_buf[4][3]~1502 dataout_buf[4][0] } { 0.000ns 1.288ns 0.730ns 0.767ns 1.991ns 0.682ns } { 0.000ns 0.914ns 0.740ns 0.511ns 0.200ns 1.243ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 74 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 74; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns dataout_buf\[4\]\[0\] 2 REG LC_X5_Y3_N4 5 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y3_N4; Fanout = 5; REG Node = 'dataout_buf\[4\]\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk dataout_buf[4][0] } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk dataout_buf[4][0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout dataout_buf[4][0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 74 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 74; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns cnt\[6\] 2 REG LC_X3_Y2_N1 4 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X3_Y2_N1; Fanout = 4; REG Node = 'cnt\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk cnt[6] } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt[6] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk dataout_buf[4][0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout dataout_buf[4][0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt[6] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 66 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 76 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.066 ns" { cnt[6] Equal9~290 Equal9~292 Equal9~293 dataout_buf[4][3]~1502 dataout_buf[4][0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.066 ns" { cnt[6] Equal9~290 Equal9~292 Equal9~293 dataout_buf[4][3]~1502 dataout_buf[4][0] } { 0.000ns 1.288ns 0.730ns 0.767ns 1.991ns 0.682ns } { 0.000ns 0.914ns 0.740ns 0.511ns 0.200ns 1.243ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk dataout_buf[4][0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout dataout_buf[4][0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt[6] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataout\[2\] en\[4\]~reg0 20.435 ns register " "Info: tco from clock \"clk\" to destination pin \"dataout\[2\]\" through register \"en\[4\]~reg0\" is 20.435 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 74 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 74; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns en\[4\]~reg0 2 REG LC_X4_Y3_N2 7 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y3_N2; Fanout = 7; REG Node = 'en\[4\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk en[4]~reg0 } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk en[4]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout en[4]~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 27 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.711 ns + Longest register pin " "Info: + Longest register to pin delay is 16.711 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns en\[4\]~reg0 1 REG LC_X4_Y3_N2 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y3_N2; Fanout = 7; REG Node = 'en\[4\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { en[4]~reg0 } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.354 ns) + CELL(0.914 ns) 2.268 ns Selector0~980 2 COMB LC_X4_Y3_N0 1 " "Info: 2: + IC(1.354 ns) + CELL(0.914 ns) = 2.268 ns; Loc. = LC_X4_Y3_N0; Fanout = 1; COMB Node = 'Selector0~980'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.268 ns" { en[4]~reg0 Selector0~980 } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.511 ns) 3.562 ns Selector0~982 3 COMB LC_X4_Y3_N6 8 " "Info: 3: + IC(0.783 ns) + CELL(0.511 ns) = 3.562 ns; Loc. = LC_X4_Y3_N6; Fanout = 8; COMB Node = 'Selector0~982'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.294 ns" { Selector0~980 Selector0~982 } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.764 ns) + CELL(0.511 ns) 5.837 ns Selector3~147 4 COMB LC_X6_Y3_N2 1 " "Info: 4: + IC(1.764 ns) + CELL(0.511 ns) = 5.837 ns; Loc. = LC_X6_Y3_N2; Fanout = 1; COMB Node = 'Selector3~147'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.275 ns" { Selector0~982 Selector3~147 } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 6.342 ns Selector3~148 5 COMB LC_X6_Y3_N3 8 " "Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 6.342 ns; Loc. = LC_X6_Y3_N3; Fanout = 8; COMB Node = 'Selector3~148'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.505 ns" { Selector3~147 Selector3~148 } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.818 ns) + CELL(0.200 ns) 8.360 ns WideOr1~21 6 COMB LC_X2_Y3_N8 14 " "Info: 6: + IC(1.818 ns) + CELL(0.200 ns) = 8.360 ns; Loc. = LC_X2_Y3_N8; Fanout = 14; COMB Node = 'WideOr1~21'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.018 ns" { Selector3~148 WideOr1~21 } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.256 ns) 12.616 ns dataout\[2\]\$latch 7 COMB LOOP LC_X6_Y3_N4 2 " "Info: 7: + IC(0.000 ns) + CELL(4.256 ns) = 12.616 ns; Loc. = LC_X6_Y3_N4; Fanout = 2; COMB LOOP Node = 'dataout\[2\]\$latch'" { { "Info" "ITDB_PART_OF_SCC" "dataout\[2\]\$latch LC_X6_Y3_N4 " "Info: Loc. = LC_X6_Y3_N4; Node \"dataout\[2\]\$latch\"" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { dataout[2]$latch } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { dataout[2]$latch } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.256 ns" { WideOr1~21 dataout[2]$latch } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.773 ns) + CELL(2.322 ns) 16.711 ns dataout\[2\] 8 PIN PIN_83 0 " "Info: 8: + IC(1.773 ns) + CELL(2.322 ns) = 16.711 ns; Loc. = PIN_83; Fanout = 0; PIN Node = 'dataout\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.095 ns" { dataout[2]$latch dataout[2] } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.914 ns ( 53.34 % ) " "Info: Total cell delay = 8.914 ns ( 53.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.797 ns ( 46.66 % ) " "Info: Total interconnect delay = 7.797 ns ( 46.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "16.711 ns" { en[4]~reg0 Selector0~980 Selector0~982 Selector3~147 Selector3~148 WideOr1~21 dataout[2]$latch dataout[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "16.711 ns" { en[4]~reg0 Selector0~980 Selector0~982 Selector3~147 Selector3~148 WideOr1~21 dataout[2]$latch dataout[2] } { 0.000ns 1.354ns 0.783ns 1.764ns 0.305ns 1.818ns 0.000ns 1.773ns } { 0.000ns 0.914ns 0.511ns 0.511ns 0.200ns 0.200ns 4.256ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk en[4]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout en[4]~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "16.711 ns" { en[4]~reg0 Selector0~980 Selector0~982 Selector3~147 Selector3~148 WideOr1~21 dataout[2]$latch dataout[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "16.711 ns" { en[4]~reg0 Selector0~980 Selector0~982 Selector3~147 Selector3~148 WideOr1~21 dataout[2]$latch dataout[2] } { 0.000ns 1.354ns 0.783ns 1.764ns 0.305ns 1.818ns 0.000ns 1.773ns } { 0.000ns 0.914ns 0.511ns 0.511ns 0.200ns 0.200ns 4.256ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 9 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jun 06 22:50:54 2009 " "Info: Processing ended: Sat Jun 06 22:50:54 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}