clock.tan.qmsg

一些Verilog学习程序B

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jun 06 22:50:51 2009 " "Info: Processing started: Sat Jun 06 22:50:51 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off clock -c clock " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clock -c clock" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTDB_FOUND_COMB_LATCHES" "" "Warning: Timing Analysis found one or more latches implemented as combinational loops" { { "Warning" "WTDB_COMB_LATCH_NODE" "dataout\[0\]\$latch " "Warning: Node \"dataout\[0\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "dataout\[1\]\$latch " "Warning: Node \"dataout\[1\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "dataout\[2\]\$latch " "Warning: Node \"dataout\[2\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "dataout\[3\]\$latch " "Warning: Node \"dataout\[3\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "dataout\[4\]\$latch " "Warning: Node \"dataout\[4\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "dataout\[5\]\$latch " "Warning: Node \"dataout\[5\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "dataout\[6\]\$latch " "Warning: Node \"dataout\[6\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis found one or more latches implemented as combinational loops" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dataout\[6\]\$latch " "Info: Node \"dataout\[6\]\$latch\"" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dataout\[5\]\$latch " "Info: Node \"dataout\[5\]\$latch\"" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dataout\[4\]\$latch " "Info: Node \"dataout\[4\]\$latch\"" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}