clock.fit.qmsg

一些Verilog学习程序B

{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0 0 "Started processing fast register assignments" 0 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:03 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Info: Fitter placement operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "15.390 ns register pin " "Info: Estimated most critical path is register to pin delay of 15.390 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns en\[3\]~reg0 1 REG LAB_X4_Y3 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y3; Fanout = 7; REG Node = 'en\[3\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { en[3]~reg0 } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.232 ns) + CELL(0.200 ns) 1.432 ns Selector0~977 2 COMB LAB_X4_Y3 4 " "Info: 2: + IC(1.232 ns) + CELL(0.200 ns) = 1.432 ns; Loc. = LAB_X4_Y3; Fanout = 4; COMB Node = 'Selector0~977'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.432 ns" { en[3]~reg0 Selector0~977 } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.380 ns) + CELL(0.200 ns) 3.012 ns Selector3~145 3 COMB LAB_X5_Y3 1 " "Info: 3: + IC(1.380 ns) + CELL(0.200 ns) = 3.012 ns; Loc. = LAB_X5_Y3; Fanout = 1; COMB Node = 'Selector3~145'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.580 ns" { Selector0~977 Selector3~145 } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.380 ns) + CELL(0.200 ns) 4.592 ns Selector3~146 4 COMB LAB_X6_Y3 1 " "Info: 4: + IC(1.380 ns) + CELL(0.200 ns) = 4.592 ns; Loc. = LAB_X6_Y3; Fanout = 1; COMB Node = 'Selector3~146'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.580 ns" { Selector3~145 Selector3~146 } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.740 ns) 5.772 ns Selector3~147 5 COMB LAB_X6_Y3 1 " "Info: 5: + IC(0.440 ns) + CELL(0.740 ns) = 5.772 ns; Loc. = LAB_X6_Y3; Fanout = 1; COMB Node = 'Selector3~147'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.180 ns" { Selector3~146 Selector3~147 } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.266 ns) + CELL(0.914 ns) 6.952 ns Selector3~148 6 COMB LAB_X6_Y3 8 " "Info: 6: + IC(0.266 ns) + CELL(0.914 ns) = 6.952 ns; Loc. = LAB_X6_Y3; Fanout = 8; COMB Node = 'Selector3~148'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.180 ns" { Selector3~147 Selector3~148 } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.333 ns) + CELL(0.914 ns) 9.199 ns WideOr3~13 7 COMB LAB_X2_Y3 2 " "Info: 7: + IC(1.333 ns) + CELL(0.914 ns) = 9.199 ns; Loc. = LAB_X2_Y3; Fanout = 2; COMB Node = 'WideOr3~13'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.247 ns" { Selector3~148 WideOr3~13 } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.540 ns) 10.739 ns dataout\[6\]\$latch 8 COMB LOOP LAB_X3_Y4 2 " "Info: 8: + IC(0.000 ns) + CELL(1.540 ns) = 10.739 ns; Loc. = LAB_X3_Y4; Fanout = 2; COMB LOOP Node = 'dataout\[6\]\$latch'" { { "Info" "ITDB_PART_OF_SCC" "dataout\[6\]\$latch LAB_X3_Y4 " "Info: Loc. = LAB_X3_Y4; Node \"dataout\[6\]\$latch\"" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { dataout[6]$latch } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { dataout[6]$latch } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.540 ns" { WideOr3~13 dataout[6]$latch } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.329 ns) + CELL(2.322 ns) 15.390 ns dataout\[6\] 9 PIN PIN_77 0 " "Info: 9: + IC(2.329 ns) + CELL(2.322 ns) = 15.390 ns; Loc. = PIN_77; Fanout = 0; PIN Node = 'dataout\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.651 ns" { dataout[6]$latch dataout[6] } "NODE_NAME" } } { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.030 ns ( 45.68 % ) " "Info: Total cell delay = 7.030 ns ( 45.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.360 ns ( 54.32 % ) " "Info: Total interconnect delay = 8.360 ns ( 54.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.390 ns" { en[3]~reg0 Selector0~977 Selector3~145 Selector3~146 Selector3~147 Selector3~148 WideOr3~13 dataout[6]$latch dataout[6] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "11 11 " "Info: Average interconnect usage is 11% of the available device resources. Peak interconnect usage is 11%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x0_y0 x8_y5 " "Info: The peak interconnect region extends from location x0_y0 to location x8_y5" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Info: Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dataout\[7\] VCC " "Info: Pin dataout\[7\] has VCC driving its datain port" {  } { { "clock.v" "" { Text "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.v" 7 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "dataout\[7\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { dataout[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { dataout[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jun 06 22:50:39 2009 " "Info: Processing ended: Sat Jun 06 22:50:39 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Info: Elapsed time: 00:00:16" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.fit.smsg " "Info: Generated suppressed messages file E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}