📄 clock.fit.rpt
字号:
; 1 Clock enable ; 4 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 9.39) ; Number of LABs (Total = 18) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 2 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 3 ;
; 10 ; 8 ;
; 11 ; 0 ;
; 12 ; 1 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 1 ;
; 16 ; 1 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 6.67) ; Number of LABs (Total = 18) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 3 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 1 ;
; 6 ; 2 ;
; 7 ; 3 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 3 ;
; 11 ; 0 ;
; 12 ; 2 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 9.78) ; Number of LABs (Total = 18) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 3 ;
; 4 ; 1 ;
; 5 ; 2 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 1 ;
; 11 ; 2 ;
; 12 ; 3 ;
; 13 ; 0 ;
; 14 ; 2 ;
; 15 ; 0 ;
; 16 ; 0 ;
; 17 ; 0 ;
; 18 ; 0 ;
; 19 ; 1 ;
; 20 ; 0 ;
; 21 ; 0 ;
; 22 ; 1 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+---------------------+
; Option ; Setting ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As input tri-stated ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+---------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Sat Jun 06 22:50:24 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off clock -c clock
Info: Selected device EPM240GT100C5 for design "clock"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EPM240GT100I5 is compatible
Info: Device EPM570GT100C5 is compatible
Info: Device EPM570GT100I5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 12
Info: Automatically promoted signal "WideOr1~21" to use Global clock
Info: Automatically promoted signal "rst" to use Global clock
Info: Pin "rst" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:03
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:03
Info: Estimated most critical path is register to pin delay of 15.390 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y3; Fanout = 7; REG Node = 'en[3]~reg0'
Info: 2: + IC(1.232 ns) + CELL(0.200 ns) = 1.432 ns; Loc. = LAB_X4_Y3; Fanout = 4; COMB Node = 'Selector0~977'
Info: 3: + IC(1.380 ns) + CELL(0.200 ns) = 3.012 ns; Loc. = LAB_X5_Y3; Fanout = 1; COMB Node = 'Selector3~145'
Info: 4: + IC(1.380 ns) + CELL(0.200 ns) = 4.592 ns; Loc. = LAB_X6_Y3; Fanout = 1; COMB Node = 'Selector3~146'
Info: 5: + IC(0.440 ns) + CELL(0.740 ns) = 5.772 ns; Loc. = LAB_X6_Y3; Fanout = 1; COMB Node = 'Selector3~147'
Info: 6: + IC(0.266 ns) + CELL(0.914 ns) = 6.952 ns; Loc. = LAB_X6_Y3; Fanout = 8; COMB Node = 'Selector3~148'
Info: 7: + IC(1.333 ns) + CELL(0.914 ns) = 9.199 ns; Loc. = LAB_X2_Y3; Fanout = 2; COMB Node = 'WideOr3~13'
Info: 8: + IC(0.000 ns) + CELL(1.540 ns) = 10.739 ns; Loc. = LAB_X3_Y4; Fanout = 2; COMB LOOP Node = 'dataout[6]$latch'
Info: Loc. = LAB_X3_Y4; Node "dataout[6]$latch"
Info: 9: + IC(2.329 ns) + CELL(2.322 ns) = 15.390 ns; Loc. = PIN_77; Fanout = 0; PIN Node = 'dataout[6]'
Info: Total cell delay = 7.030 ns ( 45.68 % )
Info: Total interconnect delay = 8.360 ns ( 54.32 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 11% of the available device resources. Peak interconnect usage is 11%
Info: The peak interconnect region extends from location x0_y0 to location x8_y5
Info: Fitter routing operations ending: elapsed time is 00:00:02
Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
Info: Pin dataout[7] has VCC driving its datain port
Info: Quartus II Fitter was successful. 0 errors, 1 warning
Info: Processing ended: Sat Jun 06 22:50:39 2009
Info: Elapsed time: 00:00:16
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in E:/EPM240学习板B/Verilog/综合实验/数字时钟/clock.fit.smsg.
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