train.tan.rpt

基于FPGA火车状态机的实现方法

; N/A   ; None         ; 4.189 ns   ; sensor3 ; state.Bin   ; clock    ;
; N/A   ; None         ; 4.185 ns   ; sensor3 ; state.Ain   ; clock    ;
; N/A   ; None         ; 4.128 ns   ; sensor2 ; state.Bin   ; clock    ;
; N/A   ; None         ; 4.115 ns   ; sensor1 ; state.Ain   ; clock    ;
; N/A   ; None         ; 3.928 ns   ; sensor1 ; state.ABout ; clock    ;
; N/A   ; None         ; 3.903 ns   ; sensor4 ; state.ABout ; clock    ;
; N/A   ; None         ; 3.762 ns   ; sensor3 ; state.Astop ; clock    ;
; N/A   ; None         ; 3.731 ns   ; sensor2 ; state.ABout ; clock    ;
; N/A   ; None         ; 3.720 ns   ; sensor1 ; state.Astop ; clock    ;
; N/A   ; None         ; 3.704 ns   ; sensor2 ; state.Ain   ; clock    ;
; N/A   ; None         ; 3.583 ns   ; sensor1 ; state.Bin   ; clock    ;
; N/A   ; None         ; 3.514 ns   ; sensor4 ; state.Bin   ; clock    ;
; N/A   ; None         ; 3.495 ns   ; sensor4 ; state.Ain   ; clock    ;
; N/A   ; None         ; 3.482 ns   ; sensor4 ; state.Bstop ; clock    ;
; N/A   ; None         ; 3.457 ns   ; sensor2 ; state.Bstop ; clock    ;
+-------+--------------+------------+---------+-------------+----------+


+------------------------------------------------------------------------+
; tco                                                                    ;
+-------+--------------+------------+-------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From        ; To      ; From Clock ;
+-------+--------------+------------+-------------+---------+------------+
; N/A   ; None         ; 7.199 ns   ; state.Astop ; switch2 ; clock      ;
; N/A   ; None         ; 7.190 ns   ; state.Astop ; switch1 ; clock      ;
; N/A   ; None         ; 6.817 ns   ; state.Bin   ; switch2 ; clock      ;
; N/A   ; None         ; 6.808 ns   ; state.Bin   ; switch1 ; clock      ;
; N/A   ; None         ; 6.603 ns   ; state.Astop ; dirA[0] ; clock      ;
; N/A   ; None         ; 6.330 ns   ; state.Bstop ; dirB[0] ; clock      ;
+-------+--------------+------------+-------------+---------+------------+


+----------------------------------------------------------------------------+
; th                                                                         ;
+---------------+-------------+-----------+---------+-------------+----------+
; Minimum Slack ; Required th ; Actual th ; From    ; To          ; To Clock ;
+---------------+-------------+-----------+---------+-------------+----------+
; N/A           ; None        ; -3.227 ns ; sensor2 ; state.Bstop ; clock    ;
; N/A           ; None        ; -3.252 ns ; sensor4 ; state.Bstop ; clock    ;
; N/A           ; None        ; -3.265 ns ; sensor4 ; state.Ain   ; clock    ;
; N/A           ; None        ; -3.284 ns ; sensor4 ; state.Bin   ; clock    ;
; N/A           ; None        ; -3.353 ns ; sensor1 ; state.Bin   ; clock    ;
; N/A           ; None        ; -3.474 ns ; sensor2 ; state.Ain   ; clock    ;
; N/A           ; None        ; -3.490 ns ; sensor1 ; state.Astop ; clock    ;
; N/A           ; None        ; -3.501 ns ; sensor2 ; state.ABout ; clock    ;
; N/A           ; None        ; -3.532 ns ; sensor3 ; state.Astop ; clock    ;
; N/A           ; None        ; -3.673 ns ; sensor4 ; state.ABout ; clock    ;
; N/A           ; None        ; -3.698 ns ; sensor1 ; state.ABout ; clock    ;
; N/A           ; None        ; -3.885 ns ; sensor1 ; state.Ain   ; clock    ;
; N/A           ; None        ; -3.898 ns ; sensor2 ; state.Bin   ; clock    ;
; N/A           ; None        ; -3.955 ns ; sensor3 ; state.Ain   ; clock    ;
; N/A           ; None        ; -3.959 ns ; sensor3 ; state.Bin   ; clock    ;
; N/A           ; None        ; -4.085 ns ; sensor3 ; state.ABout ; clock    ;
+---------------+-------------+-----------+---------+-------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
    Info: Processing started: Tue Jul 10 13:11:29 2012
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off train -c train --timing_analysis_only
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" Internal fmax is restricted to 450.05 MHz between source register "state.Bin" and destination register "state.Bin"
    Info: fmax restricted to clock pin edge rate 2.222 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.165 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X94_Y15_N9; Fanout = 4; REG Node = 'state.Bin'
            Info: 2: + IC(0.537 ns) + CELL(0.150 ns) = 0.687 ns; Loc. = LCCOMB_X94_Y15_N2; Fanout = 1; COMB Node = 'Selector2~0'
            Info: 3: + IC(0.244 ns) + CELL(0.150 ns) = 1.081 ns; Loc. = LCCOMB_X94_Y15_N8; Fanout = 1; COMB Node = 'Selector2~1'
            Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 1.165 ns; Loc. = LCFF_X94_Y15_N9; Fanout = 4; REG Node = 'state.Bin'
            Info: Total cell delay = 0.384 ns ( 32.96 % )
            Info: Total interconnect delay = 0.781 ns ( 67.04 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clock" to destination register is 2.680 ns
                Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_U30; Fanout = 5; CLK Node = 'clock'
                Info: 2: + IC(1.291 ns) + CELL(0.537 ns) = 2.680 ns; Loc. = LCFF_X94_Y15_N9; Fanout = 4; REG Node = 'state.Bin'
                Info: Total cell delay = 1.389 ns ( 51.83 % )
                Info: Total interconnect delay = 1.291 ns ( 48.17 % )
            Info: - Longest clock path from clock "clock" to source register is 2.680 ns
                Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_U30; Fanout = 5; CLK Node = 'clock'
                Info: 2: + IC(1.291 ns) + CELL(0.537 ns) = 2.680 ns; Loc. = LCFF_X94_Y15_N9; Fanout = 4; REG Node = 'state.Bin'
                Info: Total cell delay = 1.389 ns ( 51.83 % )
                Info: Total interconnect delay = 1.291 ns ( 48.17 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "state.ABout" (data pin = "sensor3", clock pin = "clock") is 4.315 ns
    Info: + Longest pin to register delay is 7.031 ns
        Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_AB25; Fanout = 4; PIN Node = 'sensor3'
        Info: 2: + IC(5.305 ns) + CELL(0.419 ns) = 6.556 ns; Loc. = LCCOMB_X94_Y15_N6; Fanout = 1; COMB Node = 'Selector0~0'
        Info: 3: + IC(0.241 ns) + CELL(0.150 ns) = 6.947 ns; Loc. = LCCOMB_X94_Y15_N16; Fanout = 1; COMB Node = 'Selector0~1'
        Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 7.031 ns; Loc. = LCFF_X94_Y15_N17; Fanout = 3; REG Node = 'state.ABout'
        Info: Total cell delay = 1.485 ns ( 21.12 % )
        Info: Total interconnect delay = 5.546 ns ( 78.88 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clock" to destination register is 2.680 ns
        Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_U30; Fanout = 5; CLK Node = 'clock'
        Info: 2: + IC(1.291 ns) + CELL(0.537 ns) = 2.680 ns; Loc. = LCFF_X94_Y15_N17; Fanout = 3; REG Node = 'state.ABout'
        Info: Total cell delay = 1.389 ns ( 51.83 % )
        Info: Total interconnect delay = 1.291 ns ( 48.17 % )
Info: tco from clock "clock" to destination pin "switch2" through register "state.Astop" is 7.199 ns
    Info: + Longest clock path from clock "clock" to source register is 2.680 ns
        Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_U30; Fanout = 5; CLK Node = 'clock'
        Info: 2: + IC(1.291 ns) + CELL(0.537 ns) = 2.680 ns; Loc. = LCFF_X94_Y15_N27; Fanout = 4; REG Node = 'state.Astop'
        Info: Total cell delay = 1.389 ns ( 51.83 % )
        Info: Total interconnect delay = 1.291 ns ( 48.17 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 4.269 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X94_Y15_N27; Fanout = 4; REG Node = 'state.Astop'
        Info: 2: + IC(0.511 ns) + CELL(0.438 ns) = 0.949 ns; Loc. = LCCOMB_X94_Y15_N20; Fanout = 2; COMB Node = 'switch1~0'
        Info: 3: + IC(0.718 ns) + CELL(2.602 ns) = 4.269 ns; Loc. = PIN_W23; Fanout = 0; PIN Node = 'switch2'
        Info: Total cell delay = 3.040 ns ( 71.21 % )
        Info: Total interconnect delay = 1.229 ns ( 28.79 % )
Info: th for register "state.Bstop" (data pin = "sensor2", clock pin = "clock") is -3.227 ns
    Info: + Longest clock path from clock "clock" to destination register is 2.680 ns
        Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_U30; Fanout = 5; CLK Node = 'clock'
        Info: 2: + IC(1.291 ns) + CELL(0.537 ns) = 2.680 ns; Loc. = LCFF_X94_Y15_N23; Fanout = 3; REG Node = 'state.Bstop'
        Info: Total cell delay = 1.389 ns ( 51.83 % )
        Info: Total interconnect delay = 1.291 ns ( 48.17 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 6.173 ns
        Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_AB26; Fanout = 4; PIN Node = 'sensor2'
        Info: 2: + IC(5.107 ns) + CELL(0.150 ns) = 6.089 ns; Loc. = LCCOMB_X94_Y15_N22; Fanout = 1; COMB Node = 'Selector4~1'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.173 ns; Loc. = LCFF_X94_Y15_N23; Fanout = 3; REG Node = 'state.Bstop'
        Info: Total cell delay = 1.066 ns ( 17.27 % )
        Info: Total interconnect delay = 5.107 ns ( 82.73 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 139 megabytes
    Info: Processing ended: Tue Jul 10 13:11:30 2012
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01