train.tan.rpt

基于FPGA火车状态机的实现方法

Classic Timing Analyzer report for train
Tue Jul 10 13:11:30 2012
Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Parallel Compilation
  6. Clock Setup: 'clock'
  7. tsu
  8. tco
  9. th
 10. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                  ;
+------------------------------+-------+---------------+------------------------------------------------+-------------+-------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From        ; To          ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+-------------+-------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 4.315 ns                                       ; sensor3     ; state.ABout ; --         ; clock    ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 7.199 ns                                       ; state.Astop ; switch2     ; clock      ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -3.227 ns                                      ; sensor2     ; state.Bstop ; --         ; clock    ; 0            ;
; Clock Setup: 'clock'         ; N/A   ; None          ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; state.Bin   ; state.Bin   ; clock      ; clock    ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;             ;             ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+-------------+-------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C70F896C6       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 2           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2 processors           ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock'                                                                                                                                                                           ;
+-------+------------------------------------------------+-------------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From        ; To          ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; state.Bin   ; state.Bin   ; clock      ; clock    ; None                        ; None                      ; 1.165 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; state.ABout ; state.Bin   ; clock      ; clock    ; None                        ; None                      ; 1.071 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; state.Bin   ; state.ABout ; clock      ; clock    ; None                        ; None                      ; 1.070 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; state.ABout ; state.Ain   ; clock      ; clock    ; None                        ; None                      ; 1.067 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; state.Astop ; state.Ain   ; clock      ; clock    ; None                        ; None                      ; 0.947 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; state.Ain   ; state.ABout ; clock      ; clock    ; None                        ; None                      ; 0.936 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; state.Bstop ; state.Bin   ; clock      ; clock    ; None                        ; None                      ; 0.820 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; state.Ain   ; state.Bstop ; clock      ; clock    ; None                        ; None                      ; 0.812 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; state.Bin   ; state.Astop ; clock      ; clock    ; None                        ; None                      ; 0.775 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; state.Bstop ; state.Bstop ; clock      ; clock    ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; state.ABout ; state.ABout ; clock      ; clock    ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; state.Ain   ; state.Ain   ; clock      ; clock    ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; state.Astop ; state.Astop ; clock      ; clock    ; None                        ; None                      ; 0.407 ns                ;
+-------+------------------------------------------------+-------------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------+
; tsu                                                                  ;
+-------+--------------+------------+---------+-------------+----------+
; Slack ; Required tsu ; Actual tsu ; From    ; To          ; To Clock ;
+-------+--------------+------------+---------+-------------+----------+
; N/A   ; None         ; 4.315 ns   ; sensor3 ; state.ABout ; clock    ;