train.v

基于FPGA火车状态机的实现方法

				// Example Verilog State machine to control trains File: Tcontrol.v
module train (reset, clock, sensor1, sensor2, sensor3, sensor4, sensor5, 
				switch1, switch2, switch3, dirA, dirB,CLOCK_50);
				// This section defines state machine inputs and outputs
				// No modifications should be needed in this section
	input reset, clock, sensor1, sensor2, sensor3, sensor4, sensor5,CLOCK_50;
	output switch1, switch2, switch3;
	output [1:0] dirA, dirB;
	reg switch1, switch2;
				// dirA and dirB are 2-bit logic vectors(i.e. an array of 2 bits)
	reg [1:0] dirA, dirB;
	reg [2:0] state;
				// This code describes how the state machine operates
				// This section will need changes for a different state machine
		/*wire button;

  reg [10:0]cnt;
  reg clk_25k;

  always@(posedge CLOCK_50)
  begin
  if(cnt==11'd999)
  begin
  clk_25k <= 1'b1;
  cnt <= cnt +1'b1;
  end
  else if(cnt==11'd1999)
  begin
  cnt <=11'd0;
  clk_25k <= 1'b0;
  end
  else 
  cnt <= cnt +1'b1;
  end 
  
    debounce u1 (
  .iCLK(clk_25k), 
  .iBUTTON(clock), 
  .oBUTTON(button) 
  ); */

	parameter ABout = 0, Ain = 1, Bin = 2, Astop = 3, Bstop = 4;
	
		
				// This section describes how the state machine behaves
				// this process runs once every time reset or the clock changes
	
	always @(negedge clock or negedge reset)
		begin
				// Reset to this state (i.e. asynchronous reset)
			if (!reset)
				state = ABout;
			else
				// posedge clock means positive clock edge 
				//This section will execute once on each positive clock edge
				//Signal assignments in this section will generate D flip-flops
				// Case statement to determine next state
			case (state)
				ABout: 
						// This Case checks both sensor1 and sensor2 bits
					case (sensor12)
						2'b 00: state = ABout;
						2'b 01: state = Bin;
						2'b 10: state = Ain;
						2'b 11: state = Ain;
							// Default case is needed here
						default: state = ABout;
					endcase
				Ain: 
					case (sensor24)
						2'b 00: state = Ain;
						2'b 01: state = ABout;
						2'b 10: state = Bstop;
						2'b 11: state = ABout;
						default: state = ABout;
					endcase
				Bin: 
					case (sensor13)
						2'b 00: state = Bin;
						2'b 01: state = ABout;
						2'b 10: state = Astop;
						2'b 11: state = ABout;
						default: state = ABout;
					endcase
				Astop: 
					if (sensor3) 
						state = Ain;
					else
						state = Astop;
				Bstop: 
					if (sensor4)
						state = Bin;
					else
						state = Bstop;
				default: state = ABout;		
			endcase
		end
				// combine sensor bits for case statements above
				// { } operators combine bits

				// These outputs do not depend on the state 
				wire [1:0] sensor12 = {sensor1, sensor2};
	wire [1:0] sensor13 = {sensor1, sensor3};
	wire [1:0] sensor24 = {sensor2, sensor4};

	wire switch3 = 0;
				// Outputs that depend on state, use state to select value
				// Be sure to specify every output for every state 
				// values will not default to zero!
	always @(state)
		begin
			case (state)
				ABout:
					begin
						switch1 = 0;
						switch2 = 0;
						dirA = 2'b 01;
						dirB = 2'b 01;
					end
				Ain:
					begin
						switch1 = 0;
						switch2 = 0;
						dirA = 2'b 01;
						dirB = 2'b 01;
					end
				Bin:
					begin
						switch1 = 1;
						switch2 = 1;
						dirA = 2'b 01;
						dirB = 2'b 01;
					end
				Astop:
					begin
						switch1 = 1;
						switch2 = 1;
						dirA = 2'b 00;
						dirB = 2'b 01;
					end
				Bstop:
					begin
						switch1 = 0;
						switch2 = 0;
						dirA = 2'b 01;
						dirB = 2'b 00;
					end
				default:
					begin
						switch1 = 0;
						switch2 = 0;
						dirA = 2'b 00;
						dirB = 2'b 00;
					end
			endcase
		end	
	endmodule