saa7113_prp.c.bak

基于SAA7113的MPEG-4程序

/*
Special notes for CMOS sensor data capture.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/compatmac.h>
#include <linux/hdreg.h>
#include <linux/vmalloc.h>
#include <linux/fs.h>
#include <linux/module.h>
#include <linux/blkpg.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <linux/i2c-id.h>
#include <linux/slab.h>
#include <asm/io.h>
#include <linux/mm.h>
#include <linux/wrapper.h>
#include <asm/dma.h>
#include <linux/miscdevice.h>

#include <asm/arch/mx2.h>

#include "type.h"
#include "videomode.h"



#define  EMMA_PRP_IRQ    51
#define  SAA7113_ADDR     0x4A



static int   IN_Y_WIDTH_SIZE;
static int   IN_Y_HIGHT_SIZE;

static int   OUT_Y_WIDTH_SIZE;
static int   OUT_Y_HIGHT_SIZE;
static int   Y_BUFFER_SIZE;

// functions and interface
static int csi_prp_open(struct inode *inode, struct file *filp);
static int csi_prp_release(struct inode *inode, struct file *filp);
static ssize_t csi_prp_read(struct file *filp, char *buf, size_t size, loff_t *l);
static ssize_t csi_prp_write(struct file *filp, const char *buf, size_t size, loff_t *l);
static int csi_prp_ioctl (struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg);


static UINT32 gMajor;
static int mode = 0;

static DECLARE_WAIT_QUEUE_HEAD(gDctWaitQueue);	/* waiting for buffer */

/* Global variables */
UINT8          *pDstYAddr;
UINT8          *pDstUAddr;
UINT8          *pDstVAddr;

dma_addr_t	    phyDestYAddr;
dma_addr_t	    phyDestUAddr;
dma_addr_t	    phyDestVAddr;

UINT8          *pDstYAddr2;
UINT8          *pDstUAddr2;
UINT8          *pDstVAddr2;

dma_addr_t	    phyDestYAddr2;
dma_addr_t	    phyDestUAddr2;
dma_addr_t	    phyDestVAddr2;


struct file_operations csi_prp_fops = {
	open:         csi_prp_open,
	release:       csi_prp_release,
	read:         csi_prp_read,
	write:	     csi_prp_write,
	ioctl:	     csi_prp_ioctl,
};

void delay500ns()
{
	int i;
	for(i=0;i<100;i++);
}

void delay1us()
{
	delay500ns();
	delay500ns();
}
void delay2us()
{
	delay1us();
	delay1us();
}
void delay5us()
{
	delay2us();
	delay2us();
	delay1us();
}

void delay8us()
{
	delay5us();
	delay2us();
	delay1us();
}
void delay10us()
{
	delay5us();
	delay5us();
}

SINT32 set_sda_input()
{
	
	/* 
	 * PE3 : SDA
	 * PE4 : SCL
	 */
	_reg_GPIO_DDIR(GPIOE) &= ~0x00000008;
	
	return 0;
}

SINT32 set_sda_output()
{
	
	/* 
	 * PE3 : SDA
	 * PE4 : SCL
	 */
	_reg_GPIO_DDIR(GPIOE) |= 0x00000008;
	
	return 0;
}

SINT32 set_sda_value(UINT8 flag)
{
	
	/* 
	 * PE3 : SDA
	 * PE4 : SCL
	 */
	 
	if(flag)
		_reg_GPIO_DR(GPIOE) |= 0x00000008;
	else
		_reg_GPIO_DR(GPIOE) &= ~0x0000008;
	
	return 0;
}


SINT32 set_scl_high()
{
	
	/* 
	 * PE3 : SDA
	 * PE4 : SCL
	 */
	_reg_GPIO_DR(GPIOE) |= 0x00000010;
	
	return 0;
}

SINT32 set_scl_low()
{
	
	/* 
	 * PA15 : SDA
	 * PA16 : SCL
	 */
	_reg_GPIO_DR(GPIOE) &= ~0x00000010;
	
	return 0;
}


/* Read sda status */
UINT8 get_sda_value()
{
	if(_reg_GPIO_SSR(GPIOE) & 0x00000008)
		return 0x01;
	else
		return 0x00;

}

/* SCCB write */	
void sccb_write(UINT8 reg, UINT8 data)
{
	int i;
	UINT8 addr;
		
	addr = SAA7113_ADDR;
	
	set_sda_value(1);
	set_scl_high();
	
	delay10us();
	set_sda_value(0);    // Issue start command
	
	/* Send ID address */
	for(i=0;i<8;i++)
	{
		delay10us();
		set_scl_low();    // First clock start
	
		delay500ns();
		set_sda_value((addr >> (7-i)) & 0x01);
	
		delay10us();
		set_scl_high();   
	}
	
	delay10us();
	set_scl_low();    // The Ninth clock start
	
	delay1us();
	set_sda_input();
	
	delay8us();
	set_scl_high();   // Dont't care bit
	
	delay10us();
	set_scl_low();
	
	delay2us();
	set_sda_output();
	
	/* Send sub address */
	for(i=0;i<8;i++)
	{
		
	
		delay500ns();
		set_sda_value((reg >> (7-i)) & 0x01);
	
		delay10us();
		set_scl_high();   
		
		delay10us();
		set_scl_low();   
	}
	
	delay1us();
	set_sda_input();
	
	delay8us();
	set_scl_high();   // Dont't care bit
	
	delay10us();
	set_scl_low();
	
	delay2us();
	set_sda_output();
	static DECLARE_WAIT_QUEUE_HEAD(g_capture_wait);
	/* Send sub address */
	for(i=0;i<8;i++)
	{
			
		delay500ns();
		set_sda_value((data >> (7-i)) & 0x01);
	
		delay10us();
		set_scl_high();   
		
		delay10us();
		set_scl_low();   
	}
	
	delay1us();
	set_sda_input();
	
	delay8us();
	set_scl_high();   // Dont't care bit
	
	delay10us();
	set_scl_low();
	
	delay2us();
	set_sda_output();
	set_sda_value(0);
	
	delay10us();
	set_scl_high(); 
	
	delay10us();
	set_sda_value(1);  // Stop
	
	return;
	
	
}

/* SCCB write */	
void sccb_read(UINT8 reg, UINT8 *data)
{
	int i;
	UINT8 addr,ret;
	
	ret = 0;
	*data = 0;
	
	/* 2-phases write */	
	addr = SAA7113_ADDR;
	
	set_sda_value(1);
	set_scl_high();
	
	delay10us();
	set_sda_value(0);    // Issue start command
	
	/* Send ID address */
	for(i=0;i<8;i++)
	{
		delay10us();
		set_scl_low();    // First clock start
	
		delay500ns();
		set_sda_value((addr >> (7-i)) & 0x01);
	
		delay10us();
		set_scl_high();   
	}
	
	delay10us();
	set_scl_low();    // The Ninth clock start
	
	delay1us();
	set_sda_input();
	
	delay8us();
	set_scl_high();   // Dont't care bit
	
	delay10us();
	set_scl_low();
	
	delay2us();
	set_sda_output();
	
	/* Send sub address */
	for(i=0;i<8;i++)
	{
		
	
		delay500ns();
		set_sda_value((reg >> (7-i)) & 0x01);
	
		delay10us();
		set_scl_high();   
		
		delay10us();
		set_scl_low();   
	}
	
	delay1us();
	set_sda_input();
	
	delay8us();
	set_scl_high();   // Dont't care bit
	
	delay10us();
	set_scl_low();
	
	delay2us();
	set_sda_output();
	set_sda_value(0);
	
	delay10us();
	set_scl_high(); 
	
	delay10us();
	set_sda_value(1);  // Stop 2-phases write
	
	/****************************************************************/
	/* 2-phases read */	
	addr = SAA7113_ADDR + 1;
	
	set_sda_value(1);
	set_scl_high();
	
	delay10us();
	set_sda_value(0);    // Issue start command
	
	/* Send ID address */
	for(i=0;i<8;i++)
	{
		delay10us();
		set_scl_low();    // First clock start
	
		delay500ns();
		set_sda_value((addr >> (7-i)) & 0x01);
	
		delay10us();
		set_scl_high();   
	}
	
	delay10us();
	set_scl_low();    // The Ninth clock start
	
	delay1us();
	set_sda_input();
	
	delay8us();
	set_scl_high();   // Dont't care bit
	delay10us();
	
	for(i=0;i<8;i++)
	{
		set_scl_low();
		delay10us();
		set_scl_high();
	
		delay5us();
		ret = get_sda_value();
		*data |= (ret << (7-i));
		delay5us();
	}
	
	set_scl_low();    // The Ninth clock start
	delay1us();
	set_sda_output();
	
	delay500ns();
	set_sda_value(1);
	
	delay8us();
	set_scl_high();   // Dont't care bit
	
	delay10us();
	set_scl_low();
	
	delay5us();
	set_sda_value(0);
	
	
	delay10us();
	set_scl_high(); 
	
	delay10us();
	set_sda_value(1);  // Stop 2-phases write