motordef.h

wince开发的xbase270开发板实现电机的控制。可控制步进电机和直流电机的运转时间

#pragma once

#define GPIO_81		( 1u << 17 )		
#define GPIO_82		( 1u << 18 )
#define GPIO_83		( 1u << 19 ) //0x00080000
#define GPIO_84		( 1u << 20 ) //0x00100000
#define GPIO_53		( 1u << 21 )

#define GPIO_BASE_U_VIRTUAL 0x40E00000 // GPIO Virtual Base address


// GPIO definition start
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
typedef struct {
	unsigned int GPLR_x; // 0x40E00000 Pin Level Registers
	unsigned int GPLR_y; // 0x40E00004
	unsigned int GPLR_z; // 0x40E00008
	unsigned int GPDR_x; // 0x40E0000C Pin Direction Registers
	unsigned int GPDR_y; // 0x40E00010
	unsigned int GPDR_z; // 0x40E00014
	unsigned int GPSR_x; // 0x40E00018 Pin Output Set Registers
	unsigned int GPSR_y; // 0x40E0001C
	unsigned int GPSR_z; // 0x40E00020
	unsigned int GPCR_x; // 0x40E00024 Pin Output Clear Registers
	unsigned int GPCR_y; // 0x40E00028
	unsigned int GPCR_z; // 0x40E0002C
	unsigned int GRER_x; // 0x40E00030 Rising Edge Detect Enable Registers
	unsigned int GRER_y; // 0x40E00034
	unsigned int GRER_z; // 0x40E00038
	unsigned int GFER_x; // 0x40E0003C Falling Edge Detect Enable Registers
	unsigned int GFER_y; // 0x40E00040
	unsigned int GFER_z; // 0x40E00044
	unsigned int GEDR_x; // 0x40E00048 Edge Detect Status Registers
	unsigned int GEDR_y; // 0x40E0004C
	unsigned int GEDR_z; // 0x40E00050
	unsigned int GAFR0_x; // 0x40E00054 Alternate Function Registers
	unsigned int GAFR1_x; // 0x40E00058
	unsigned int GAFR0_y; // 0x40E0005C
	unsigned int GAFR1_y; // 0x40E00060
	unsigned int GAFR0_z; // 0x40E00064
	unsigned int GAFR1_z; // 0x40E00068
} GPIO_REGS, *PGPIO_REGS;

//
// OSSR Bits
//
#define OST_BASE_PHYSICAL 0x40A00000

#define OSSR_M0 (0x1 << 0)
#define OSSR_M1 (0x1 << 1)
#define OSSR_M2 (0x1 << 2)
#define OSSR_M3 (0x1 << 3)

#define TIMERTICK 4

//
// OIER Bits
//
#define OIER_E0 (0x1 << 0)
#define OIER_E1 (0x1 << 1)
#define OIER_E2 (0x1 << 2)
#define OIER_E3 (0x1 << 3)

//
// OST (os timer)
//
typedef struct
{
    unsigned long    osmr0;          //OS timer match register 0
    unsigned long    osmr1;          //OS timer match register 1
    unsigned long    osmr2;          //OS timer match register 2
    unsigned long    osmr3;          //OS timer match register 3
    unsigned long    oscr;           //OS timer counter register
    unsigned long    ossr;           //OS timer status register
    unsigned long    ower;           //OS timer watchdog enable register
    unsigned long    oier;           //OS timer interrupt enable register
} OST_REGS, *POST_REGS;