eregdef.h.svn-base

realtek的8186芯片ADSL路由AP源代码

#define C0_CALG_C3		0xc		/* 0x60000000 to 0x7FFFFFFF					*/
#define C0_CALG_C4		0x10	/* 0x80000000 to 0x9FFFFFFF					*/
#define C0_CALG_C5		0x14	/* 0xA0000000 to 0xBFFFFFFF					*/
#define C0_CALG_C6		0x18	/* 0xC0000000 to 0xDFFFFFFF					*/
#define C0_CALG_C7		0x1c	/* 0xE0000000 to 0xFFFFFFFF					*/
#define C0_CALG_M0		0x0		/* Cached, write-through, no write-allocate */
#define C0_CALG_M1		0x1		/* Cached, write-through, write-allocate	*/
#define	C0_CALG_M2		0x2		/* Uncahced									*/
#define C0_CALG_M3		0x3		/* Cached, write-back, write-allocate		*/

/* BSO compatible */
#define ST_KUO			0x00000020	/* Kernel/User mode, old */
#define ST_IEO			0x00000010	/* Interrupt Enable, old */
#define ST_KUP			0x00000008	/* Kernel/User mode, previous */
#define ST_IEP			0x00000004	/* Interrupt Enable, previous */
#define ST_KUC			0x00000002	/* Kernel/User mode, current */
#define ST_IEC			0x00000001	/* Interrupt Enable, current */

/* Cause Register */
#define CAUSE_BD		0x80000000	/* Branch Delay */
#define CAUSE_CEMASK	0x30000000	/* Coprocessor Error */
#define CAUSE_CESHIFT	28			/* Right justify CE  */
#define CAUSE_DW		0x02000000	/* DWatch Reg. matced on a Watch except. */
#define CAUSE_IW		0x01000000	/* IWatch Reg. matced on a Watch except. */
#define CAUSE_IV		0x00800000	/* Exception Vec. (200) for interrupt.	*/
#define CAUSE_IPMASK	0x0000ff00	/* Interrupt Pending */
#define CAUSE_IPSHIFT	8			/* Right justify IP  */
#define CAUSE_IP8		0x00008000	/*  (Intr5) */
#define CAUSE_IP7		0x00004000	/*  (Intr4) */
#define CAUSE_IP6		0x00002000	/*  (Intr3) */
#define CAUSE_IP5		0x00001000	/*  (Intr2) */
#define CAUSE_IP4		0x00000800	/*  (Intr1) */
#define CAUSE_IP3		0x00000400	/*  (Intr0) */
#define CAUSE_SW2		0x00000200	/*  (Software Interrupt 1) */
#define CAUSE_SW1		0x00000100	/*  (Software Interrupt 0) */
#define CAUSE_EXCMASK	0x0000007c	/* Exception Code */
#define CAUSE_EXCSHIFT	2			/* Right justify EXC */

/* Exception Code */
#define EXC_INT			(0 << 2)	/* External interrupt */
#define EXC_MOD			(1 << 2)	/* TLB modification */
#define EXC_TLBL		(2 << 2)    /* TLB miss (Load or Ifetch) */
#define EXC_IBOUND		(2 << 2)	/* Replacing TLB in 4650	*/
#define EXC_TLBS		(3 << 2)	/* TLB miss (Save) */
#define EXC_DBOUND		(3 << 2)	/* Replacing TLB in 4650	*/
#define EXC_ADEL		(4 << 2)    /* Address error (Load or Ifetch) */
#define EXC_ADES		(5 << 2)	/* Address error (Store) */
#define EXC_IBE			(6 << 2)	/* Bus error (Ifetch) */
#define EXC_DBE			(7 << 2)	/* Bus error (data load or store) */
#define EXC_SYS			(8 << 2)	/* System call */
#define EXC_BP			(9 << 2)	/* Break point */
#define EXC_RI			(10 << 2)	/* Reserved instruction */
#define EXC_CPU			(11 << 2)	/* Coprocessor unusable */
#define EXC_OVF			(12 << 2)	/* Arithmetic overflow */
#define EXC_TR			(13 << 2)	/* Trap Exception		*/
#define	EXC_FPE			(15 << 2)	/* Floating-Point Exception	*/
#define EXC_WATCH		(23 << 23)	/* Watch Exception			*/

/* 3041 */
#define BUSCTRL_LOCK	0x80000000
#define BUSCTRL_MEM		0x0C000000
#define BUSCTRL_ED		0x03000000
#define BUSCTRL_IO		0x00C00000
#define BUSCTRL_BE16	0x00200000
#define BUSCTRL_BE		0x00080000
#define BUSCTRL_BTA		0x0000C000
#define BUSCTRL_DMA		0x00002000
#define BUSCTRL_TC		0x00001000
#define BUSCTRL_BR		0x00000800




/* Normalized Exception Codes */
#if defined( R3K )||defined( r3k )

#define EX_UNKNOWN_INTERRUPT		0
#define	EX_TLB_MODIFIED				1
#define	EX_TLB_MISS_LF				2
#define	EX_TLB_MISS_S				3
#define	EX_ADDRESS_ERROR_LF			4
#define	EX_ADDRESS_ERROR_S			5
#define	EX_BUS_ERROR_F				6
#define	EX_BUS_ERROR_LS				7
#define	EX_UNKNOWN_SYSCALL			8
#define	EX_UNKNOWN_BREAK			9
#define	EX_RESERVED_INSTRUCTION		10
#define	EX_COPROCESSOR_UNUSABLE		11
#define	EX_OVERFLOW					12
#define	EX_RESERVED13				13
#define	EX_RESERVED14				14
#define	EX_RESERVED15				15

#endif

#if defined( R4K )||defined( r4k )

#define EX_UNKNOWN_INTERRUPT		0
#define	EX_TLB_MODIFIED				1
#define	EX_TLB_MISS_LF				2
#define	EX_TLB_MISS_S				3
#define	EX_ADDRESS_ERROR_LF			4
#define	EX_ADDRESS_ERROR_S			5
#define	EX_BUS_ERROR_F				6
#define	EX_BUS_ERROR_LS				7
#define	EX_UNKNOWN_SYSCALL			8
#define	EX_UNKNOWN_BREAK			9
#define	EX_RESERVED_INSTRUCTION		10
#define	EX_COPROCESSOR_UNUSABLE		11
#define	EX_OVERFLOW					12
#define	EX_TRP						13
#define	EX_RESERVED14				14
#define	EX_FPE						15

#endif

/* CACHE opcode	*/
#if defined( R4K )||defined( r4k )

/* primary cache	*/
#define	I_INDEX_INVALIDATE			0x0
#define D_INDEX_WRITEBACK_INVALIDATE		0x1
#define	I_INDEX_LOAD_TAG			0x4
#define	D_INDEX_LOAD_TAG			0x5
#define	I_INDEX_STORE_TAG			0x8
#define	D_INDEX_STORE_TAG			0x9
#define D_CREATE_DIRTY_EXCLUSIVE	0xd
#define I_HIT_INVALIDATE			0x10
#define D_HIT_INVALIDATE			0x11
#define	I_FILL						0x14
#define	D_HIT_WRITEBACK_INVALIDATE	0x15
#define	I_HIT_WRITEBACK				0x18
#define	D_HIT_WRITEBACK				0x19

/* secondary cache	*/
#define S_INDEX_LOAD_TAG			0x7
#define S_INDEX_STORE_TAG			0xb
#define S_VALID_CLEAR				0x3
#define S_PAGE_INVALIDATE			0x17
#define S_CACHE_PAGE_SIZE			0x1000
#define S_CACHE_UNIT_SIZE			0x80000
#endif

#define HI_HALF(x)	((x) >> 16)
#define LO_HALF(x)	((x) & 0xffff)



/* Floating-Point Control register bits */
#define CSR_C			0x00800000
#define CSR_EXC			0x0003f000
#define CSR_EE			0x00020000
#define CSR_EV			0x00010000
#define CSR_EZ			0x00008000
#define CSR_EO			0x00004000
#define CSR_EU			0x00002000
#define CSR_EI			0x00001000
#define CSR_TV			0x00000800
#define CSR_TZ			0x00000400
#define CSR_TO			0x00000200
#define CSR_TU			0x00000100
#define CSR_TI			0x00000080
#define CSR_SV			0x00000040
#define CSR_SZ			0x00000020
#define CSR_SO			0x00000010
#define CSR_SU			0x00000008
#define CSR_SI			0x00000004
#define CSR_RM			0x00000003


/*
** PRID Values for various processors:
*/
#define PRID_3000		0x00000230 /* + 3051/52/81/71 */
#define PRID_3041		0x00000700
#define PRID_3041A		0x00000701
#define PRID_3041FX		0x00000710
#define PRID_36100		0x00000710

#define PRID_33000		0			/* 33050/33020 */
#define PRID_33300		0x00000A0A
#define PRID_33310		0x00000B0A

#define PRID_30100		0x00002100	/* Philips PR30100 (MR300 core) */

#define PRID_4640		0x00002200
#define PRID_4650		0x00002200
#define PRID_4000		0x00000400
#define PRID_4200		0x00000a00
#define PRID_4300		0x00000b00
#define PRID_4400		0x00000400	/* should 4400 = 4000 in that sense ? */
#define PRID_4600		0x00002000
#define PRID_4700		0x00002100

#define PRID_5000		0x00002300
#define PRID_52XX		0x00002800
#define PRID_5230		0x00002800
#define PRID_5260		0x00002800
#define PRID_7000		0x00002700

#define PRID_64475		0x00003000
#define PRID_64474		0x00003000
#define PRID_6447X		0x00003000

#define PRID_32364      0x00002600

#define PRID_MASK		0x0000ff00


/*-------------------------------------------------------------------
**
** Memory Mapped Registers - IDT 36100 Family
**
**-------------------------------------------------------------------
*/
#define TM41_PRESCALE_COUNT 0xffffe900
#define TM41_TIMER0_COUNT	0xffffe910
#define TM41_TIMER0_COMPARE	0xffffe914
#define TM41_TIMER0_PWM		0xffffe918
#define TM41_TIMER0_CONTROL	0xffffe91c
#define TM41_TIMER1_COUNT	0xffffe920
#define TM41_TIMER1_COMPARE	0xffffe924
#define TM41_TIMER1_CONTROL	0xffffe92c
#define TM41_TIMER2_COUNT	0xffffe930
#define TM41_TIMER2_COMPARE	0xffffe934
#define TM41_TIMER2_CONTROL	0xffffe93c

#define PIO41_GLOBAL_LOCK	0xffffea00
#define PIO41_DATA0			0xffffea10
#define PIO41_DC0			0xffffea10
#define PIO41_ESC0			0xffffea10
#define PIO41_DATA1			0xffffea10
#define PIO41_DC1			0xffffea10
#define PIO41_ESC1			0xffffea10

#define INT41_EICR			0xffffeb00
#define INT41_EIPR0			0xffffeb10
#define INT41_EIMR0			0xffffeb14
#define INT41_EIPR1			0xffffeb20
#define INT41_EIMR1			0xffffeb24
#define INT41_EIPR2			0xffffeb30
#define INT41_EIMR2			0xffffeb34

#define DBG41_TRACE_ADDR	0xffffe500
#define DBG41_TRACE_CONTROL	0xffffe504
#define DBG41_DEBUG_CONTROL	0xffffe508




/*-------------------------------------------------------------------
**
** Defines for Lexra's LX-4080 core
**
**-------------------------------------------------------------------
*/
#if defined( LX4080 ) || defined( LX4080_CORE )
#define C0_CCTL		$20		/* Cache Control */
#define CCTL_DIvl	0x00000001	/* Invalidate Dcache */
#define CCTL_IIvl	0x00000002	/* Invalidate Icache/IRAM */
#define CCTL_ILk	0x00000004
#define CCTL_ILkM	0x00000008

/* Coprocessor 3 Control Registers */
#define C3_CON		$0

/* Coprocessor 3 General Registers */
#define C3_IWBASE	$0	/* IW Base Address [31:10] */
#define C3_IWTOP	$1	/* IW Top Address [15:4] */
#define C3_DWBASE	$4	/* DW Base Address [31:10] */
#define C3_DWTOP	$5	/* DW Top Address [15:4] */
#define C3_CNT0LO	$8	/* Counter 0 [31:0] */
#define C3_CNT0HI	$9	/* Counter 0 [47:32] */
#define C3_CNT1LO	$10	/* Counter 1 [31:0] */
#define C3_CNT1HI	$11	/* Counter 1 [47:32] */
#define C3_CNT2LO	$12	/* Counter 2 [31:0] */
#define C3_CNT2HI	$13	/* Counter 2 [47:32] */
#define C3_CNT3LO	$14	/* Counter 3 [31:0] */
#define C3_CNT3HI	$15	/* Counter 3 [47:32] */

#endif





/*-------------------------------------------------------------------
**
** Defines for Philips MR300 CORE / PR30100 OCP processor
**
**-------------------------------------------------------------------
*/

/* MR300 core registers and bit definitions */
#define MR_CCR			$16
#define MR_CONFIG		$17

#define CCR_ICD			0x1
#define CCR_ICI			0x2
#define CCR_EII			0x4
#define CCR_ICL			0x8
#define CCR_DCD			0x10
#define CCR_DCI			0x20
#define CCR_EDI			0x40
#define CCR_DBD			0x80
#define CCR_DCL			0x100

#define CONFIG_IS		0x1
#define CONFIG_SP		0x2
#define CONFIG_ILS		0xC
#define CONFIG_DLS		0x30
#define CONFIG_RVE		0x100
#define CONFIG_VS		0x3000
#define CONFIG_SMIO		0xFF0000

/* R4650,R4700,R5000	*/
#define	CONFIG_IC_MASK	0xE00	/* indicates i-cache size	*/
#define CONFIG_DC_MASK	0x1C0	/* indicates d-cache size	*/
#define CONFIG_IB_MASK	0x20	/* indicates i-cache line size	*/
#define CONFIG_DB_MASK	0x10	/* indicates d-cache line szie	*/
#define	CONFIG_BE		0x8000	/* endianness				*/
#define	CONFIG_SS_MASK	0x00300000	/* secondary cache size	*/
#define	CONFIG_SE		0x1000	/* secondary cache enable	*/

/* OCP (PR30100) internal memory mapped registers internals */
#define	OCP_REG_BASE	0xb0c00000

/* register offsets from the base address */
#define OCP_MCR0		0
#define OCP_MCR1		4
#define OCP_MCR2		8
#define OCP_MCR3		0xc
#define OCP_IO_DIR		0xa0
#define OCP_IO_DATA_OUT 0xac

#define	TB_CONF_REG		0xbe000080



/*-------------------------------------------------------------------
**  CPU sub groups (e.g. chip makers) (Used by osboot and rss)
**  BIT Field
**------------------------------------------------------------------- 
*/
#define R3000_CORE		1		/* R3000/R3010 */
#define IDT_R3000_CORE	2		/* IDT 3051/52/81/71/41/41fx */
								/* Philips MR300 core */
#define LR33000_CORE	3		/* LR33000/33050/33020 */
#define R4000_CORE		4		/* R4000 */
#define LX4080_CORE		5		/* Lexra 4080  */
#define IDT32_CORE		6		/* IDT MIPS32 core  */

#define	K0BASE		0x80000000
#define	K0SIZE		0x20000000
#define	K1BASE		0xA0000000
#define	K1SIZE		0x20000000

#define	R_VEC		(K1BASE+0x1fc00000)	/* reset vector */