eregdef.h.svn-base

realtek的8186芯片ADSL路由AP源代码

/**************************************************************************/
/*                              EREGDEF.H                                 */
/**************************************************************************/
/*  Copyright(c) 1987-99 Embedded Performance, Inc.. All rights reserved  */
/*																		  */
/*  This software is the property of Embedded Performance, Inc (EPI)	  */
/*  which specifically  grants the user the right to modify, and use	  */
/*  this software provided this notice is not removed or altered.  All	  */
/*  other rights are reserved by EPI.									  */
/*                                                                        */
/**************************************************************************/
/*                                                                        */
/*  Embedded Performance, Inc. (EPI) makes no warranty  of any kind,      */
/*  express or implied, with regard to this software.  In no event shall  */
/*  EPI be liable for incidental or consequential damages in connection   */
/*  with or arising from  the furnishing,  performance, or use of this    */
/*  software.                                                             */
/*                                                                        */
/**************************************************************************/
/*																		  */
/*  This file defines various register names and chip addresses.          */
/*																		  */
/**************************************************************************/
/*																		  */
/*  Internal to EPI note:  This file is maintained in both scm and scmr4k */
/*  Please make any changes to both places.                               */
/*																		  */
/**************************************************************************/


#ifdef _ASMLANGUAGE		/* set automatically by assembler */

#define zero $0	
#define AT	$at		/* assembler temp */
#define v0	$2		/* function return value0 */
#define v1	$3      /* function return value1 */
#define a0	$4		/* argument registers 0-3 */
#define a1	$5
#define a2	$6
#define a3	$7
#define t0	$8
#define t1	$9
#define t2	$10
#define t3	$11
#define t4	$12
#define t5	$13
#define t6	$14
#define t7	$15
#define s0	$16
#define s1	$17
#define s2	$18
#define s3	$19
#define s4	$20
#define s5	$21
#define s6	$22
#define s7	$23
#define t8	$24	
#define t9	$25
#define k0	$26		/* kernel temporary */
#define k1	$27		/* kernel reserved */
#define gp	$28		/* global data pointer */
#define sp	$29		/* stack pointer */
#define s8	$30		/* one more callee saved */
#define ra	$31		/* return address */

/*----- hardware registers names ---------------------*/
#define r0	$0	
#define r1	$at	
#define r2	$2	
#define r3	$3
#define r4	$4	
#define r5	$5
#define r6	$6
#define r7	$7
#define r8	$8	
#define r9	$9
#define r10	$10
#define r11	$11
#define r12	$12
#define r13	$13
#define r14	$14
#define r15	$15
#define r16	$16		
#define r17	$17
#define r18	$18
#define r19	$19
#define r20	$20
#define r21	$21
#define r22	$22
#define r23	$23
#define r24	$24		
#define r25	$25
#define r26	$26		
#define r27	$27
#define r28	$28		
#define r29	$29		
#define r30	$30		
#define r31	$31		


/*----- coprocessor 0 register names ----------------*/

/* generic names */
#define C0_0		$0
#define C0_1		$1
#define C0_2		$2
#define C0_3		$3
#define C0_4		$4
#define C0_5		$5
#define C0_6		$6
#define C0_7		$7
#define C0_8		$8
#define C0_9		$9
#define C0_10		$10
#define C0_11		$11
#define C0_12		$12
#define C0_13		$13
#define C0_14		$14
#define C0_15		$15
#define C0_16		$16
#define C0_17		$17
#define C0_18		$18
#define C0_19		$19
#define C0_20		$20
#define C0_21		$21
#define C0_22		$22
#define C0_23		$23
#define C0_24		$24
#define C0_25		$25
#define C0_26		$26
#define C0_27		$27
#define C0_28		$28
#define C0_29		$29
#define C0_30		$30
#define C0_31		$31

/* common register names of C0 */
#define C0_INDEX	$0
#define C0_INX		$0		/* TLB Index */
#define C0_IBASE	$0		/* Instruction Addr. Space Base	*/
#define	C0_IBOUND	$1		/* Instruction Addr. Space Bound	*/
#define C0_RANDOM	$1
#define C0_RAND		$1		/* TLB Random */
#define C0_ENTRYLO	$2
#define C0_TLBLO	$2		/* TLB EntryLo */
#define C0_DBASE	$2		/* Data Address Space Base		*/
#define	C0_ENTRYLO0	$2
#define C0_DBOUND	$3		/* Data Address Space Bound		*/
#define C0_ENTRYLO1	$3
#define C0_CONTEXT	$4
#define C0_CTEXT	$4		/* Context */
#define	C0_PAGEMASK	$5
#define	C0_WIRED	$6
#define C0_BADVADDR	$8
#define C0_COUNT	$9		/* R4K Timer	*/
#define C0_ENTRYHI	$10
#define C0_TLBHI	$10		/* TLB EntryHi */
#define C0_COMPARE	$11		/* R4K: acts as s timer	*/
#define C0_SR		$12
#define C0_STATUS	$12
#define C0_CAUSE	$13
#define C0_EPC		$14
#define C0_PRID		$15
#if	defined(R4K)||defined(r4k)
#define C0_CONFIG	$16		/* Device Configuration Information. Read ONLY	*/
#else
#define C0_CONFIG   $3		/* IDT 3081/71/41 specific registers */
#endif	/* R4K	*/
#define C0_CALG		$17		/* Cache Attributes	*/
#define C0_LLADDR	$17
#define C0_IWATCH	$18		/* R4K		*/
#define C0_DWATCH	$19
#define	C0_XCONTEXT	$20
#define C0_ECC		$26		/* Error Checking and Correcting	*/
#define C0_CACHEERR	$27		/* Cache parity error: read only	*/
#define C0_TAGLO	$28		/* Cache Addressing	*/
#define C0_TAGHI	$29
#define C0_ERROREPC	$30



/* IDT 3041 specific registers */
#define C0_BUSCTRL  $2
#define C0_COUNT	$9
#define C0_PORTSIZE $10
#define C0_COMPARE  $11



/*----- coprocessor 1 control register names ---------*/
#define C1_FCR0		$0		/* Implementation/Revision register */
#define FPA_IRR		$0
#define C1_FGR0		$0
#define C1_FGR1		$1
#define C1_FGR2		$2
#define C1_FGR3		$3
#define C1_FGR4		$4
#define C1_FGR5		$5
#define C1_FGR6		$6
#define C1_FGR7		$7
#define C1_FGR8		$8
#define C1_FGR9		$9
#define C1_FGR10	$10
#define C1_FGR11	$11
#define C1_FGR12	$12
#define C1_FGR13	$13
#define C1_FGR14	$14
#define C1_FGR15	$15
#define C1_FGR16	$16
#define C1_FGR17	$17
#define C1_FGR18	$18
#define C1_FGR19	$19
#define C1_FGR20	$20
#define C1_FGR21	$21
#define C1_FGR22	$22
#define C1_FGR23	$23
#define C1_FGR24	$24
#define C1_FGR25	$25
#define C1_FGR26	$26
#define C1_FGR27	$27
#define C1_FGR28	$28
#define C1_FGR29	$29
#define C1_FGR30	$30
#define C1_FGR31	$31
#define FPA_CSR		$31		/* Control/Status register */
#define C1_FCR31	$31


/*----- misc. assembly language defines -----------------------------*/
#define global globl


/*
** LEAF: start of a leaf routine define
*/
#define	LEAF(proc)	\
	.globl	proc;	\
	.ent	proc;	\
proc:;				\
	.frame	sp,0,ra

/*
** END: end of the procedure define
*/
#define	END(proc) .end	proc



#endif  /* LANGUAGE_ASSEMBLY */


/* Exception vector locations */

#if defined( R4K )||defined( r4k )
#define TLB_MISS_VECT 	0x80000000
#define XTLB_MISS_VECT 	0x80000080
#define CACHE_ERROR_VECT 0xA0000100
#define GENERAL_VECT	0x80000180
#define INTERRUPT_VECT	0x80000200
#else
#define UTLB_MISS_VECT 	0x80000000
#define GENERAL_VECT	0x80000080
#endif




/* Status Register */
#if defined( R4K ) || defined( r4k )
#define SR_CUMASK		0xf0000000	/* Coprocessor usable bits */
#define	SR_CU3			0x80000000	/* Coprocessor 3 usable */
#define SR_CU2			0x40000000	/* coprocessor 2 usable */
#define SR_CU1			0x20000000	/* Coprocessor 1 usable */
#define SR_CU0			0x10000000	/* Coprocessor 0 usable */
#define SR_FR			0x04000000	/* Enable Additional Floating-point Reg.*/
#define SR_RE			0x02000000	/* Reverse Endian Bit	*/
#define SR_DL			0x01000000	/* Data Cache Lock: refill into A disable*/
#define SR_IL			0x00800000	/* Instr. Cahe Lock: Refill to A disabled*/
#define SR_BEV			0x00400000	/* Bootstrap Exception Vector */
#define SR_SR			0x00100000	/* Soft Reset or NMI occurring bit	*/
#define SR_CH			0x00040000	/* Cache Hit(: 1)/Miss(: 0) */
#define SR_CE			0x00020000	/* ECC register set(: 1) */
#define SR_DE			0x00010000	/* Cache parity exception:dis/enabled(1/0)*/

#define SR_IMASK		0x0000ff00	/* Interrupt Mask */
#define SR_IMASK8		0x00000000	/* Interrupt Mask level=8 */
#define SR_IMASK7		0x00008000	/* Interrupt Mask level=7 */
#define SR_IMASK6		0x0000c000	/* Interrupt Mask level=6 */
#define SR_IMASK5		0x0000e000	/* Interrupt Mask level=5 */
#define SR_IMASK4		0x0000f000	/* Interrupt Mask level=4 */
#define SR_IMASK3		0x0000f800	/* Interrupt Mask level=3 */
#define SR_IMASK2		0x0000fc00	/* Interrupt Mask level=2 */
#define SR_IMASK1		0x0000fe00	/* Interrupt Mask level=1 */
#define SR_IMASK0		0x0000ff00	/* Interrupt Mask level=0 */

#define SR_IBIT8		0x00008000	/*  (Intr5) */
#define SR_IBIT7		0x00004000	/*  (Intr4) */
#define SR_IBIT6		0x00002000	/*  (Intr3) */
#define SR_IBIT5		0x00001000	/*  (Intr2) */
#define SR_IBIT4		0x00000800	/*  (Intr1) */
#define SR_IBIT3		0x00000400	/*  (Intr0) */
#define SR_IBIT2		0x00000200	/*  (Software Interrupt 1) */
#define SR_IBIT1		0x00000100	/*  (Software Interrupt 0) */

#define	SR_KX			0x00000080
#define SR_SX			0x00000040
#define SR_UX			0x00000020	/* 1=64 bit enabled; 0=32 bit enabled	*/
#define SR_UM			0x00000010	/* 0=Kernal Mode / 1=User Mode	*/
#define SR_KSU			0x00000018	/* Supervisor Mode.  4600/4700	*/
#define SR_ERL			0x00000004	/* Error Level: 0-normal/1-error	*/
#define SR_EXL			0x00000002	/* Exception Level: 0-normal/1-exception */
#define SR_IE			0x00000001	/* Interrupt Enable, current */
#else	/* end of R4K, start of R3K:	*/
#define SR_CUMASK		0xf0000000	/* Coprocessor usable bits */
#define	SR_CU3			0x80000000	/* Coprocessor 3 usable */
#define SR_CU2			0x40000000	/* coprocessor 2 usable */
#define SR_CU1			0x20000000	/* Coprocessor 1 usable */
#define SR_CU0			0x10000000	/* Coprocessor 0 usable */
#define SR_BEV			0x00400000	/* Bootstrap Exception Vector */
#define SR_TS			0x00200000	/* TLB shutdown */
#define SR_PE			0x00100000	/* Parity Error */
#define SR_CM			0x00080000	/* Cache Miss */
#define SR_PZ			0x00040000	/* Parity Zero */
#define SR_SWC			0x00020000	/* Swap Caches */
#define SR_ISC			0x00010000	/* Isolate Cache */

#define SR_IMASK		0x0000ff00	/* Interrupt Mask */
#define SR_IMASK8		0x00000000	/* Interrupt Mask level=8 */
#define SR_IMASK7		0x00008000	/* Interrupt Mask level=7 */
#define SR_IMASK6		0x0000c000	/* Interrupt Mask level=6 */
#define SR_IMASK5		0x0000e000	/* Interrupt Mask level=5 */
#define SR_IMASK4		0x0000f000	/* Interrupt Mask level=4 */
#define SR_IMASK3		0x0000f800	/* Interrupt Mask level=3 */
#define SR_IMASK2		0x0000fc00	/* Interrupt Mask level=2 */
#define SR_IMASK1		0x0000fe00	/* Interrupt Mask level=1 */
#define SR_IMASK0		0x0000ff00	/* Interrupt Mask level=0 */

#define SR_IBIT8		0x00008000	/*  (Intr5) */
#define SR_IBIT7		0x00004000	/*  (Intr4) */
#define SR_IBIT6		0x00002000	/*  (Intr3) */
#define SR_IBIT5		0x00001000	/*  (Intr2) */
#define SR_IBIT4		0x00000800	/*  (Intr1) */
#define SR_IBIT3		0x00000400	/*  (Intr0) */
#define SR_IBIT2		0x00000200	/*  (Software Interrupt 1) */
#define SR_IBIT1		0x00000100	/*  (Software Interrupt 0) */

#define SR_KUO			0x00000020	/* Kernel/User mode, old */
#define SR_IEO			0x00000010	/* Interrupt Enable, old */
#define SR_KUP			0x00000008	/* Kernel/User mode, previous */
#define SR_IEP			0x00000004	/* Interrupt Enable, previous */
#define SR_KUC			0x00000002	/* Kernel/User mode, current */
#define SR_IEC			0x00000001	/* Interrupt Enable, current */
#endif	/*	R3K	*/


/* C0_CALG	*/
/* MX: cache mode; CX: number of bits for MX to be left shifted	in C0_CALG	*/
#define C0_CALG_C0		0x0		/* 0x00000000 to 0x1FFFFFFF					*/
#define C0_CALG_C1		0x4		/* 0x20000000 to 0x3FFFFFFF					*/
#define C0_CALG_C2		0x8		/* 0x40000000 to 0x5FFFFFFF					*/