📄 rominit.s.svn-base
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/*
* romInit.s System initialization/brings up assembly routine
*
* History:
* 2006/10/27 SH, Lee Add big model support
* 2006/10/30 SH, Lee Add determine memory configuration
*/
#define _ASMLANGUAGE
#include "eregdef.h"
#include "board.h"
.extern C_Entry
#define RELOC(toreg,address) \
bal 9f; \
9:; \
la toreg,address; \
addu toreg,ra; \
la ra,9b; \
subu toreg,ra
#define RVECENT(f,n) \
b f; nop
#define XVECENT(f,bev) \
b f; li k0,bev
/* For hard or soft reset, jump forward to handler.
otherwise, jump to hard reset entry point, unless
exception handler is called. */
.globl romInit
.set noreorder
romInit:
_romInit:
b __romInit
nop
romWarmInit:
_romWarmInit:
b __romReboot
nop
RVECENT(_romInit,2)
RVECENT(_romInit,3)
RVECENT(_romInit,4)
RVECENT(_romInit,5)
RVECENT(_romInit,6)
RVECENT(_romInit,7)
RVECENT(_romInit,8)
RVECENT(_romInit,9)
RVECENT(_romInit,10)
RVECENT(_romInit,11)
RVECENT(_romInit,12)
RVECENT(_romInit,13)
RVECENT(_romInit,14)
RVECENT(_romInit,15)
RVECENT(_romInit,16)
RVECENT(_romInit,17)
RVECENT(_romInit,18)
RVECENT(_romInit,19)
RVECENT(_romInit,20)
RVECENT(_romInit,21)
RVECENT(_romInit,22)
RVECENT(_romInit,23)
RVECENT(_romInit,24)
RVECENT(_romInit,25)
RVECENT(_romInit,26)
RVECENT(_romInit,27)
RVECENT(_romInit,28)
RVECENT(_romInit,29)
RVECENT(_romInit,30)
RVECENT(_romInit,31)
RVECENT(_romInit,33)
RVECENT(_romInit,34)
RVECENT(_romInit,35)
RVECENT(_romInit,36)
RVECENT(_romInit,37)
RVECENT(_romInit,38)
RVECENT(_romInit,39)
RVECENT(_romInit,40)
RVECENT(_romInit,41)
RVECENT(_romInit,42)
RVECENT(_romInit,43)
RVECENT(_romInit,44)
RVECENT(_romInit,45)
RVECENT(_romInit,46)
RVECENT(_romInit,47)
RVECENT(_romInit,48)
/* This needs to be at offset 0x180 */
b romExcHandle
li k0, 0x180
RVECENT(_romInit,49)
RVECENT(_romInit,50)
RVECENT(_romInit,51)
RVECENT(_romInit,52)
RVECENT(_romInit,53)
RVECENT(_romInit,54)
RVECENT(_romInit,55)
RVECENT(_romInit,56)
RVECENT(_romInit,57)
RVECENT(_romInit,58)
RVECENT(_romInit,59)
RVECENT(_romInit,60)
RVECENT(_romInit,61)
RVECENT(_romInit,62)
RVECENT(_romInit,63)
RVECENT(_romInit,64)
RVECENT(_romInit,65)
RVECENT(_romInit,66)
RVECENT(_romInit,67)
RVECENT(_romInit,68)
RVECENT(_romInit,69)
RVECENT(_romInit,70)
RVECENT(_romInit,71)
RVECENT(_romInit,72)
RVECENT(_romInit,73)
RVECENT(_romInit,74)
RVECENT(_romInit,75)
RVECENT(_romInit,76)
RVECENT(_romInit,77)
RVECENT(_romInit,78)
RVECENT(_romInit,79)
RVECENT(_romInit,80)
RVECENT(_romInit,81)
RVECENT(_romInit,82)
RVECENT(_romInit,83)
RVECENT(_romInit,84)
RVECENT(_romInit,85)
RVECENT(_romInit,86)
RVECENT(_romInit,87)
RVECENT(_romInit,88)
RVECENT(_romInit,89)
RVECENT(_romInit,90)
RVECENT(_romInit,91)
RVECENT(_romInit,92)
RVECENT(_romInit,93)
RVECENT(_romInit,94)
RVECENT(_romInit,95)
RVECENT(_romInit,96)
RVECENT(_romInit,97)
RVECENT(_romInit,98)
RVECENT(_romInit,99)
RVECENT(_romInit,100)
RVECENT(_romInit,101)
RVECENT(_romInit,102)
RVECENT(_romInit,103)
RVECENT(_romInit,104)
RVECENT(_romInit,105)
RVECENT(_romInit,106)
RVECENT(_romInit,107)
RVECENT(_romInit,108)
RVECENT(_romInit,109)
RVECENT(_romInit,110)
RVECENT(_romInit,111)
RVECENT(_romInit,112)
RVECENT(_romInit,113)
RVECENT(_romInit,114)
RVECENT(_romInit,115)
RVECENT(_romInit,116)
RVECENT(_romInit,116)
RVECENT(_romInit,118)
RVECENT(_romInit,119)
RVECENT(_romInit,120)
RVECENT(_romInit,121)
RVECENT(_romInit,122)
RVECENT(_romInit,123)
RVECENT(_romInit,124)
RVECENT(_romInit,125)
RVECENT(_romInit,126)
RVECENT(_romInit,127)
__romInit:
.set noreorder
mfc0 k0,C0_EPC # save for nvram
move k1,ra # save for nvram
mfc0 gp,C0_SR
mfc0 t7,C0_CAUSE
li v0,SR_BEV
mtc0 v0,C0_SR # state unknown on reset
mtc0 zero,C0_CAUSE # clear software interrupts
nop # paranoia
.set reorder
__romReboot:
/* second entry point -- sw reboot inherits a0 start type */
.set noreorder
li t0, SR_CU1 | SR_BEV
nop
mtc0 t0, C0_SR /* disable all interrupts fpa on, */
/* prom exception handlers */
mtc0 zero, C0_CAUSE /* clear all interrupts */
nop
.set reorder
#--- bypass copying if in RAM
bal 1f
1:
la t0, 0x10000000
and t0, ra, t0
beq t0, zero, 2f # decide if ram based on BIT28
.set noreorder
#---Disable WatchDog
li t0,0xA5800000
li t1,0xB9C0103C
sw t0,0(t1)
#---Disable GIMR/GISR
li t0,0x0000FFFF
li t1,0xB9C03010
sw t0,0(t1)
#---Reset GPIO
#ifdef MINIMODEL_SUPPORT
li t0,0x00400000 //config GPA6 to output 0
li t1,0xB9C01000
sw t0,0x00(t1)
sw zero,0x04(t1) //full low GPA6
#elif Flash_AA21_GPA5
li t0,0x00200000 //config GPA5 to output 0
li t1,0xB9C01000
sw t0,0x00(t1)
sw zero,0x04(t1) //full low GPA5
#else
li t0,0x00FF0000
li t1,0xB9C01000
sw zero,0x00(t1)
sw zero,0x04(t1)
sw t0,0x08(t1)
sw zero,0x0C(t1)
sw zero,0x10(t1)
sw zero,0x14(t1)
sw t0,0x18(t1)
sw zero,0x1C(t1)
#endif
#--- invalidate the icache and dcache with a 0->1 transition
mtc0 zero, $20
nop
nop
li t0, 0x3
mtc0 t0, $20
nop
nop
mtc0 zero, $20
nop
nop
#--- initialize and start COP3
mfc0 t0,$12
nop
or t0,0x80000000
mtc0 t0,$12
nop
nop
# disable IRAM
li t0, 0x84000000 #address without SDRAM
and t0, 0x0ffffc00 # translate to physical address
mtc3 t0, $0 # $0: i-ram base
nop
nop
li t0, 4096 - 1
mtc3 t0, $1 # $1: i-ram top
nop
nop
# disable DRAM
li t0, 0x85000000 #address without SDRAM
and t0, 0x0ffffc00 # translate to physical address
mtc3 t0, $4 # $4: d-ram base
nop
nop
li t0, 4096 - 1
mtc3 t0, $5 # $5: d-ram top
nop
nop
#--- enable icache and dcache
mtc0 $0, $20 # CCTL
nop
nop
.set reorder
#--- configure memory controller
#---this is for ASIC
#--- determine memory configuraton
li t0, 0xbfc0e000 # parameter start address
keep_search:
lw t1, 0(t0)
beq t1, 0x4265726c, found_param # is "Berl" ?
add t0, 0x40
beq t0, 0xbfc10000, default_config # not found parameter, use default
nop
b keep_search
found_param:
li a0, 0x02800000 # init mcr0
lw t1, 48(t0) # load flash size
li v0, 0xffffffff # check if parameters stored in flash is valid?
beq t1, v0, default_config # default setting in board.h MCR0
li v0, 2
li t2, 0x40000000 # mark bit30
beq t1, v0, 3f # case 2MB
sltiu v0, t1, 3 # v0 = (t1<3)?1:0
beqz v0, 4f # v0=0, goto forward 4
b memconfig # case 1MB do nothing
4:
li v0, 4
li t2, 0x80000000 # mark bit31
beq t1, v0, 3f # case 4MB
li t2, 0xc0000000 # mark bit 31&30 , case 8MB
3:
or a0, a0, t2 # set flash size
memconfig:
lw t1, 52(t0) # load mem size
li v0, 8
li t2, 0x10000000
beq t1, v0, 3f # case 8MB
sltiu v0, t1, 9 # v0 = (t1<9)?1:0
beqz v0, 4f # v0=0, case 16MB
li v0, 4 # is 4MB ?
li t2, 0x00000000 # case 4MB
beq t1, v0, 3f
b default_config # no match!?
4:
li v0, 16
li t2, 0x20000000 # case 16MB
beq t1, v0, 3f
b default_config # no match!? use default value
3:
or a0, a0, t2 # set mem size
li t1, 0xB9000000
sw a0, 0(t1) # set memory configuration
b go_ahead
default_config:
li t0,MCR0_VAL
li t1,0xB9000000
sw t0,0(t1)
go_ahead:
# li t0,MCR0_VAL
# li t1,0xB9000000
# sw t0,0(t1)
#---- determine memory configuration end here
li t0,MCR1_VAL
li t1,0xB9000004
sw t0,0(t1)
#--- this is for ASIC
li t0,MCR2_VAL
li t1,0xB9000008
sw t0,0(t1)
#--- hrchen, this is for device bus weighting
li t0,CPUC_VAL
li t1,0xB9C03000
sw t0,0(t1)
#-- Enable system clock spectrum
#-- let memory driving from 14mA to 8mA
#-- Read timing tuning from 00 to 10
li t0,0xF0257C0C
li t1,0xb9c04004
sw t0,0(t1)
#ifdef SAMSUNG_SUPPORT
li t0, 0xe825000c
li t1, 0xb9c04004
sw t0, 0(t1)
#endif
#--- shlee determine D/F version 8671 reserve bit 22
la t3,0x00400000
la t0,0xb9c04000
lw t1,0(t0)
la t3, 0x00400000
and t2, t1, t3
# -- determine D/F version 8671 reserve bit 22
#write 0 to reset PCI
li t0,SICR_VAL
li t1,0xB9C04000
# andi t2, t0, 0x00001000
# beq zero, t0, PCI_disabled
and t0,t0,~0x80000000
#--- shlee determine D/F version 8671 reserve bit 22
or t0, t2, t0
#--- determine D/F version 8671 reserve bit 22
sw t0,0(t1)
#delay for > 1ms, 0x00010000 is near 500ms
li t2, 0x00001000
DEV_reset_delay:
addi t2, t2, -1
nop
bne zero, t2, DEV_reset_delay
#--- this is for System Interface
#--- shlee determine D/F version 8671 reserve bit 22
#ifdef Flash_AA21_GPA5
or t0, t0, 0x80000020 # GPIO interface as PCI
#else
or t0, t0,0x80000000
#endif
sw t0, 0(t1)
#--- determine D/F version 8671 reserve bit 22
#-- shlee for version D/F li t0,SICR_VAL
#PCI_disabled:
#-- shlee for version D/F sw t0,0(t1)
#--- copy itself to RAM
la t0, FLASH_START
la t1, FLASH_START+0x10000
la t2, MEM_START
1: lw t3, 0(t0)
sw t3, 0(t2)
addi t0, t0, 4
addi t2, t2, 4
bne t0, t1, 1b
la t0, MEM_START
jr t0
2:
/* absolutely basic initialization to allow things to continue */
#bal basicInit
/* setup bootloader stack */
la gp, _gp /* set global ptr from cmplr */
la sp, MEM_LIMIT-8 /* set temp stack ptr */
# or sp, K1BASE /* make it uncached */
/* Init BSS spaces */
la t0, _fbss
la t1, _ebss
beq t0, t1, 2f
1: sw zero, 0(t0)
addi t0, t0, 4
bne t0, t1, 1b
2:
/* jump to SDRAM */
la t0, C_Entry
jr t0
fail:
b fail
/*******************************************************************************
*
* romExcHandle - rom based exception/interrupt handler, do nothing but hang
*/
.ent romExcHandle
romExcHandle:
hangExc:
b hangExc /* HANG UNTIL REBOOT */
.end romExcHandle
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