m5200.h

来自「MPC5200 BSP 支持ATA,USB, I2C,扩展网口」· C头文件 代码 · 共 1,062 行 · 第 1/4 页

#define PSC_ISR_IMR_IPC    (1<<15)

/* register bit definitions */

/* MR1 - mode register 1 */
#define PSC_UART_MR1_BC0	(1 << 0)	/* bits per char 0 */
#define PSC_UART_MR1_BC1	(1 << 1)	/* bits per char 1 */
#define PSC_UART_MR1_PT		(1 << 2)	/* parity type */
#define PSC_UART_MR1_PM0	(1 << 3)	/* parity mode 0 */
#define PSC_UART_MR1_PM1	(1 << 4)	/* parity mode 1 */
#define PSC_UART_MR1_ERR	(1 << 5)	/* error mode */
#define PSC_UART_MR1_RX_IRQ	(1 << 6)	/* receiver interrupt select */
#define PSC_UART_MR1_RX_RTS	(1 << 7)	/* Rx RTS control */

/* Some common modes */
#define PSC_UART_MR1_BITS_CHAR_5	0
#define PSC_UART_MR1_BITS_CHAR_6	PSC_UART_MR1_BC0
#define PSC_UART_MR1_BITS_CHAR_7	PSC_UART_MR1_BC1
#define PSC_UART_MR1_BITS_CHAR_8	(PSC_UART_MR1_BC0 \
					 | PSC_UART_MR1_BC1)
#define PSC_UART_MR1_NO_PARITY	(PSC_UART_MR1_PM1)
#define PSC_UART_MR1_PAR_MODE_MULTI	(PSC_UART_MR1_PM0 \
					 | PSC_UART_MR1_PM1)
#define PSC_UART_MR1_EVEN_PARITY	0
#define PSC_UART_MR1_ODD_PARITY	PSC_UART_MR1_PT

/* MR2 - mode register 2 */
#define PSC_UART_MR2_SB0	(1 << 0)	/* stop bit control 0 */
#define PSC_UART_MR2_SB1	(1 << 1)	/* stop bit control 1 */
#define PSC_UART_MR2_SB2	(1 << 2)	/* stop bit control 2 */
#define PSC_UART_MR2_SB3	(1 << 3)	/* stop bit control 3 */
#define PSC_UART_MR2_TX_CTS	(1 << 4)	/* Tx CTS control */
#define PSC_UART_MR2_TX_RTS	(1 << 5)	/* Tx RTS control */
#define PSC_UART_MR2_CM0	(1 << 6)	/* channel mode 0 */
#define PSC_UART_MR2_CM1	(1 << 7)	/* channel mode 1 */

/* Some common bit lengths */
#define PSC_UART_MR2_STOP_BITS_1	(PSC_UART_MR2_SB0 \
					 | PSC_UART_MR2_SB1 \
					 | PSC_UART_MR2_SB2)
#define PSC_UART_MR2_STOP_BITS_2	(PSC_UART_MR2_SB0 \
					 | PSC_UART_MR2_SB1 \
					 | PSC_UART_MR2_SB2 \
					 | PSC_UART_MR2_SB3)

/* SR - status register */
#define PSC_UART_SR_CDE		(1 << 7)	/* DCD error */
#define PSC_UART_SR_RXRDY	(1 << 8)	/* Rx ready */
#define PSC_UART_SR_FFULL	(1 << 9)	/* FIFO full */
#define PSC_UART_SR_TXRDY	(1 << 10)	/* Tx ready */
#define PSC_UART_SR_TXEMP	(1 << 11)	/* Tx empty */
#define PSC_UART_SR_OE		(1 << 12)	/* overrun error */
#define PSC_UART_SR_PE		(1 << 13)	/* parity error */
#define PSC_UART_SR_FE		(1 << 14)	/* framing error */
#define PSC_UART_SR_RB		(1 << 15)	/* received break */

/* CSR - clock select register */
#define PSC_UART_CSR_TCS0	(1 << 8)	/* Tx clock select 0 */
#define PSC_UART_CSR_TCS1	(1 << 9)	/* Tx clock select 1 */
#define PSC_UART_CSR_TCS2	(1 << 10)	/* Tx clock select 2 */
#define PSC_UART_CSR_TCS3	(1 << 11)	/* Tx clock select 3 */
#define PSC_UART_CSR_RCS0	(1 << 12)	/* Rx clock select 0 */
#define PSC_UART_CSR_RCS1	(1 << 13)	/* Rx clock select 1 */
#define PSC_UART_CSR_RCS2	(1 << 14)	/* Rx clock select 2 */
#define PSC_UART_CSR_RCS3	(1 << 15)	/* Rx clock select 3 */

#define PSC_UART_CSR_TIMER_TX	(PSC_UART_CSR_TCS0 \
				 | PSC_UART_CSR_TCS2 \
				 | PSC_UART_CSR_TCS3)
#define PSC_UART_CSR_TIMER_RX	(PSC_UART_CSR_RCS0 \
				 | PSC_UART_CSR_RCS2 \
				 | PSC_UART_CSR_RCS3)

/* CR - command register */
#define PSC_UART_CR_RC0		(1 << 0)	/* receiver control bit 0 */
#define PSC_UART_CR_RC1		(1 << 1)	/* receiver control bit 1 */
#define PSC_UART_CR_TC0		(1 << 2)	/* transmitter control bit 0 */
#define PSC_UART_CR_TC1		(1 << 3)	/* transmitter control bit 1 */
#define PSC_UART_CR_MISC0	(1 << 4)	/* misc control bit 0 */
#define PSC_UART_CR_MISC1	(1 << 5)	/* misc control bit 1 */
#define PSC_UART_CR_MISC2	(1 << 6)	/* misc control bit 2 */

/* Some common commands */
#define PSC_UART_CR_TX_ENABLE		(PSC_UART_CR_TC0)
#define PSC_UART_CR_TX_DISABLE		(PSC_UART_CR_TC1)
#define PSC_UART_CR_RX_ENABLE		(PSC_UART_CR_RC0)
#define PSC_UART_CR_RX_DISABLE		(PSC_UART_CR_RC1)
#define PSC_UART_CR_RESET_MODE_PTR	(PSC_UART_CR_MISC0)
#define PSC_UART_CR_RESET_RX		(PSC_UART_CR_MISC1)
#define PSC_UART_CR_RESET_TX		(PSC_UART_CR_MISC0 \
									| PSC_UART_CR_MISC1)
#define PSC_UART_CR_RESET_ERR		(PSC_UART_CR_MISC2)
#define PSC_UART_CR_RESET_BRK		(PSC_UART_CR_MISC0 \
									| PSC_UART_CR_MISC2)

/* ACR - auxiliary control register */
#define PSC_UART_ACR_IEC	(1 << 0)	/* input enable control */

/* IMR - interrupt mask register */
#define PSC_UART_IMR_TXRDY	(1 << 8)	/* transmitter ready */
#define PSC_UART_IMR_RXRDY	(1 << 9)	/* receiver ready */
#define PSC_UART_IMR_DB		(1 << 10)	/* delta break */
#define PSC_UART_IMR_COS	(1 << 15)	/* change of CTS state */

/* ISR - interrupt status register */
#define PSC_UART_ISR_TXRDY	(1 << 8)	/* transmitter ready */
#define PSC_UART_ISR_RXRDY	(1 << 9)	/* receiver ready */
#define PSC_UART_ISR_DB		(1 << 10)	/* delta break */
#define PSC_UART_ISR_COS	(1 << 15)	/* change of CTS state */

/* IP - input port register */
#define PSC_UART_IP_CTS		(1 << 0)	/* current CTS state */

/* OP1 - output set register */
#define PSC_UART_OP1_RTS	(1 << 0)	/* set RTS */

/* OP2 - output reset register */
#define PSC_UART_OP2_RTS	(1 << 0)	/* clear RTS */

/*-----------------------------------------------------------*/
/* FEC (see m5200FecEnd.h) 							 0x03000 */
/*-----------------------------------------------------------*/

#define MBAR_ETH				0x3000

#define ETH_BASE_ADRS			(MBAR_VALUE + MBAR_ETH)

#define FEC_EVENT_OFF       0x0004  /* interrupt event register */
#define FEC_MASK_OFF        0x0008  /* interrupt mask register */
#define FEC_CTRL_OFF        0x0024  /* FEC control register */
#define FEC_MII_SPEED_OFF   0x0044  /* MII speed register */
#define FEC_RX_CTRL_OFF     0x0084  /* rx control register */
#define FEC_TX_CTRL_OFF     0x00c4  /* tx control register */
#define FEC_ADDR_L_OFF      0x00e4  /* lower 32-bits of MAC address */
#define FEC_ADDR_H_OFF      0x00e8  /* upper 16-bits of MAC address */
#define FEC_HASH_H_OFF      0x0118  /* upper 32-bits of hash table */
#define FEC_HASH_L_OFF      0x011c  /* lower 32-bits of hash table */
#define FEC_DGR1_OFF		0x0120  
#define FEC_DGR2_OFF		0x0124  
#define FEC_XWMRK_OFF      	0x144
#define FEC_RFCNTRL_OFF		0x18C
#define FEC_RFLRFPTR_OFF	0x190
#define FEC_RFLWFPTR_OFF	0x194
#define FEC_RFALARM_OFF		0x198
#define FEC_RFRPTR_OFF		0x19C
#define FEC_RFWPTR_OFF		0x1A0
#define FEC_TFCNTRL_OFF		0x1AC
#define FEC_TFLRFPTR_OFF	0x1B0
#define FEC_TFLWFPTR_OFF	0x1B4
#define FEC_TFALARM_OFF		0x1B8
#define FEC_TFRPTR_OFF		0x1BC
#define FEC_TFWPTR_OFF		0x1C0
#define FEC_XMITFSM_OFF		0x1C8


#define FEC_EVENT			((volatile UINT32 *)(ETH_BASE_ADRS + FEC_EVENT_OFF))
#define FEC_CTRL			((volatile UINT32 *)(ETH_BASE_ADRS + FEC_CTRL_OFF))
#define FEC_MII_SPEED		((volatile UINT32 *)(ETH_BASE_ADRS + FEC_MII_SPEED_OFF))
#define FEC_RX_CTRL			((volatile UINT32 *)(ETH_BASE_ADRS + FEC_RX_CTRL_OFF))
#define FEC_TX_CTRL			((volatile UINT32 *)(ETH_BASE_ADRS + FEC_TX_CTRL_OFF))
#define FEC_ADDR_L			((volatile UINT32 *)(ETH_BASE_ADRS + FEC_ADDR_L_OFF))
#define FEC_ADDR_H			((volatile UINT32 *)(ETH_BASE_ADRS + FEC_ADDR_H_OFF))
#define FEC_HASH_L			((volatile UINT32 *)(ETH_BASE_ADRS + FEC_HASH_L_OFF))
#define FEC_HASH_H			((volatile UINT32 *)(ETH_BASE_ADRS + FEC_HASH_H_OFF))
#define FEC_DGR1			((volatile UINT32 *)(ETH_BASE_ADRS + FEC_DGR1_OFF))
#define FEC_DGR2			((volatile UINT32 *)(ETH_BASE_ADRS + FEC_DGR2_OFF))
#define FEC_XWMRK			((volatile UINT32 *)(ETH_BASE_ADRS + FEC_XWMRK_OFF))
#define FEC_RFCNTRL			((volatile UINT32 *)(ETH_BASE_ADRS + FEC_RFCNTRL_OFF))
#define FEC_RFLRFPTR		((volatile UINT32 *)(ETH_BASE_ADRS + FEC_RFLRFPTR_OFF))
#define FEC_RFLWFPTR		((volatile UINT32 *)(ETH_BASE_ADRS + FEC_RFLWFPTR_OFF))
#define FEC_RFALARM			((volatile UINT32 *)(ETH_BASE_ADRS + FEC_RFALARM_OFF))
#define FEC_RFRPTR			((volatile UINT32 *)(ETH_BASE_ADRS + FEC_RFRPTR_OFF))
#define FEC_RFWPTR			((volatile UINT32 *)(ETH_BASE_ADRS + FEC_RFWPTR_OFF))
#define FEC_TFCNTRL			((volatile UINT32 *)(ETH_BASE_ADRS + FEC_TFCNTRL_OFF))
#define FEC_TFLRFPTR		((volatile UINT32 *)(ETH_BASE_ADRS + FEC_TFLRFPTR_OFF))
#define FEC_TFLWFPTR		((volatile UINT32 *)(ETH_BASE_ADRS + FEC_TFLWFPTR_OFF))
#define FEC_TFALARM			((volatile UINT32 *)(ETH_BASE_ADRS + FEC_TFALARM_OFF))
#define FEC_TFRPTR			((volatile UINT32 *)(ETH_BASE_ADRS + FEC_TFRPTR_OFF))
#define FEC_TFWPTR			((volatile UINT32 *)(ETH_BASE_ADRS + FEC_TFWPTR_OFF))
#define FEC_XMITFSM			((volatile UINT32 *)(ETH_BASE_ADRS + FEC_XMITFSM_OFF))


/*-----------------------------------------------------------*/
/* ATA 											      0x3A00 */
/*-----------------------------------------------------------*/
#define MBAR_ATA									0x3A00
#define ATA_BASE_ADRS						  (MBAR_VALUE + MBAR_ATA)

#define ATA_HOSTCONF_OFF       		0x00
#define ATA_HOSTSTAT_OFF				  0x04
#define ATA_PIO_TIME1_OFF         0x08
#define ATA_PIO_TIME2_OFF         0x0C
#define ATA_MDMA_TIME1_OFF				0x10
#define ATA_MDMA_TIME2_OFF				0x14
#define ATA_UDMA_TIME1_OFF				0x18
#define ATA_UDMA_TIME2_OFF				0x1C
#define ATA_UDMA_TIME3_OFF				0x20
#define ATA_UDMA_TIME4_OFF				0x24
#define ATA_UDMA_TIME5_OFF				0x28
#define ATA_SHARE_COUNT_OFF       0x2C
#define ATA_FIFO_DATA_OFF					0x3C
#define ATA_FIFO_STATUS_OFF				0x40
#define ATA_FIFO_CTRL_OFF					0x44
#define	ATA_FIFO_ALARM_OFF				0x48
#define	ATA_FIFO_READPOINT_OFF		0x4C
#define	ATA_FIFO_WRITEPOINT_OFF		0x50
#define ATA_DEV_CTRL_OFF					0x5C
#define ATA_DEVICE_COMMAND_OFF		0x7C

#define ATA_HOSTCONF_SMR		0x80000000UL	/* State machine reset */
#define ATA_HOSTCONF_FR		0x40000000UL	/* FIFO Reset */
#define ATA_HOSTCONF_IE		0x02000000UL	/* Enable interrupt   in PIO */
#define ATA_HOSTCONF_IORDY	0x01000000UL	/* Drive supports IORDY protocol */

/* ATA Drive Device Control Register—MBAR + 0x3A5C */
#define ATA_DEV_CTRL_SRST		0x04000000
#define ATA_DEV_CTRL_nIEN		0x02000000

#define ATA_HOST_CONFIG			((volatile UINT32 *)(ATA_BASE_ADRS + ATA_HOSTCONF_OFF))
#define ATA_HOSTSTAT				((volatile UINT32 *)(ATA_BASE_ADRS + ATA_HOSTSTAT_OFF))
#define ATA_PIO_TIME1			  ((volatile UINT32 *)(ATA_BASE_ADRS + ATA_PIO_TIME1_OFF))
#define ATA_PIO_TIME2			  ((volatile UINT32 *)(ATA_BASE_ADRS + ATA_PIO_TIME2_OFF))
#define ATA_MDMA_TIME1			((volatile UINT32 *)(ATA_BASE_ADRS + ATA_MDMA_TIME1_OFF))
#define ATA_MDMA_TIME2			((volatile UINT32 *)(ATA_BASE_ADRS + ATA_MDMA_TIME2_OFF))
#define ATA_UDMA_TIME1			((volatile UINT32 *)(ATA_BASE_ADRS + ATA_UDMA_TIME1_OFF))
#define ATA_UDMA_TIME2			((volatile UINT32 *)(ATA_BASE_ADRS + ATA_UDMA_TIME2_OFF))
#define ATA_UDMA_TIME3			((volatile UINT32 *)(ATA_BASE_ADRS + ATA_UDMA_TIME3_OFF))
#define ATA_UDMA_TIME4			((volatile UINT32 *)(ATA_BASE_ADRS + ATA_UDMA_TIME4_OFF))
#define ATA_UDMA_TIME5			((volatile UINT32 *)(ATA_BASE_ADRS + ATA_UDMA_TIME5_OFF))
#define ATA_SHARE_COUNT			((volatile UINT32 *)(ATA_BASE_ADRS + ATA_SHARE_COUNT_OFF))
#define ATA_FIFO_DATA				((volatile UINT32 *)(ATA_BASE_ADRS + ATA_FIFO_DATA_OFF))
#define ATA_FIFO_STATUS			((volatile UINT32 *)(ATA_BASE_ADRS + ATA_FIFO_STATUS_OFF))
#define ATA_FIFO_CTRL				((volatile UINT32 *)(ATA_BASE_ADRS + ATA_FIFO_CTRL_OFF))
#define	ATA_FIFO_ALARM			((volatile UINT32 *)(ATA_BASE_ADRS + ATA_FIFO_ALARM_OFF))
#define	ATA_FIFO_READPOINT	((volatile UINT32 *)(ATA_BASE_ADRS + ATA_FIFO_READPOINT_OFF))
#define	ATA_FIFO_WRITEPOINT	((volatile UINT32 *)(ATA_BASE_ADRS + ATA_FIFO_WRITEPOINT_OFF))
#define ATA_DEV_CTRL			  ((volatile UINT32 *)(ATA_BASE_ADRS + ATA_DEV_CTRL_OFF))
#define ATA_DEVICE_COMMAND	((volatile UINT32 *)(ATA_BASE_ADRS + ATA_DEVICE_COMMAND_OFF))
#define ATA_RXTX_FIFO_ADDRESS ((volatile UINT32 *)(ATA_BASE_ADRS + ATA_FIFO_DATA_OFF))

#define ATA_DMAMODE_REG		((volatile UINT8 *)(ATA_BASE_ADRS + ATA_DEVICE_COMMAND_OFF+1))		/*8bit*/
#define ATA_DMAMODE_HUT		0x40
#define ATA_DMAMODE_FR		0x20
#define ATA_DMAMODE_FE		0x10
#define ATA_DMAMODE_IE		0x08
#define ATA_DMAMODE_UDMA	0x04
#define ATA_DMAMODE_READ	0x02
#define ATA_DMAMODE_WRITE	0x01
/*-----------------------------------------------------------*/
/* SRAM 											  0x8000 */
/*-----------------------------------------------------------*/

#define MBAR_SRAM				0x8000

#define SRAM_BASE_ADRS			(MBAR_VALUE + MBAR_SRAM)
#define SRAM_SIZE				(16*1024)
#define SRAM_ADRS(num)			((volatile UINT32*) (SRAM_BASE_ADRS + num))

#ifdef __cplusplus
}
#endif

#endif /* __INCmpc5200b */