m5200.h

来自「MPC5200 BSP 支持ATA,USB, I2C,扩展网口」· C头文件 代码 · 共 1,062 行 · 第 1/4 页

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#define PCIISR_RE				0x04000000
#define PCIISR_IA				0x02000000
#define PCIISR_TA				0x01000000

/* PCI Arbiter Register */
#define PCIARB_RESET			0x01000000

#define PCITPSR		(volatile UINT32 *)(MBAR_VALUE+0x3800)
#define PCITSAR		(volatile UINT32 *)(MBAR_VALUE+0x3804)
#define PCITTCR		(volatile UINT32 *)(MBAR_VALUE+0x3808)
#define PCITER		(volatile UINT32 *)(MBAR_VALUE+0x380C)
#define PCITNAR		(volatile UINT32 *)(MBAR_VALUE+0x3810)
#define PCITLWR		(volatile UINT32 *)(MBAR_VALUE+0x3814)
#define PCITDCR		(volatile UINT32 *)(MBAR_VALUE+0x3818)
#define PCITSR		(volatile UINT32 *)(MBAR_VALUE+0x381C)
#define PCITPDCR	(volatile UINT32 *)(MBAR_VALUE+0x3820)
#define PCITFDR		(volatile UINT32 *)(MBAR_VALUE+0x3840)
#define PCITFSR		(volatile UINT32 *)(MBAR_VALUE+0x3844)
#define PCITFCR		(volatile UINT32 *)(MBAR_VALUE+0x3848)
#define PCITFAR		(volatile UINT32 *)(MBAR_VALUE+0x384C)
#define PCITFRPR	(volatile UINT32 *)(MBAR_VALUE+0x3850)
#define PCITFWPR	(volatile UINT32 *)(MBAR_VALUE+0x3854)
#define PCIRPSR		(volatile UINT32 *)(MBAR_VALUE+0x3880)
#define PCIRSAR		(volatile UINT32 *)(MBAR_VALUE+0x3884)
#define PCIRTCR		(volatile UINT32 *)(MBAR_VALUE+0x3888)
#define PCIRER		(volatile UINT32 *)(MBAR_VALUE+0x388C)
#define PCIRNAR		(volatile UINT32 *)(MBAR_VALUE+0x3890)
#define PCIRLWR		(volatile UINT32 *)(MBAR_VALUE+0x3894)
#define PCIRDCR		(volatile UINT32 *)(MBAR_VALUE+0x3898)
#define PCIRSR		(volatile UINT32 *)(MBAR_VALUE+0x389C)
#define PCIRPDCR	(volatile UINT32 *)(MBAR_VALUE+0x38A0)
#define PCIRFDR		(volatile UINT32 *)(MBAR_VALUE+0x38C0)
#define PCIRFSR		(volatile UINT32 *)(MBAR_VALUE+0x38C4)
#define PCIRFCR		(volatile UINT32 *)(MBAR_VALUE+0x38C8)
#define PCIRFAR		(volatile UINT32 *)(MBAR_VALUE+0x38CC)
#define PCIRFRPR	(volatile UINT32 *)(MBAR_VALUE+0x38D0)
#define PCIRFWPR	(volatile UINT32 *)(MBAR_VALUE+0x38D4)

/*-----------------------------------------------------------*/
/* USB 											      0x1000 */
/*-----------------------------------------------------------*/

#define MBAR_USB			0x1000

#define USB_BASE_ADRS		(MBAR_VALUE + MBAR_USB)

/*-----------------------------------------------------------*/
/* SMDA 											  0x1200 */
/*-----------------------------------------------------------*/
/*------------------------------------------------------------*/
/* Bestcomm									0x1200 */
/*------------------------------------------------------------*/


#define MBAR_SDMA			0x1200

#define SDMA_BASE_ADRS		(MBAR_VALUE + MBAR_SDMA)

#define BESTCOMM_TASKBAR_OFF	0x00
#define SDMA_PTD_CTRL_OFF			0x10
#define BESTCOMM_PTD_OFF  		0x10
#define BESTCOMM_PEND_OFF			0x14
#define BESTCOMM_MASK_OFF			0x18
#define BESTCOMM_IPR0_OFF			0x3C
#define BESTCOMM_IPR4_OFF			0x40
#define BESTCOMM_IPR8_OFF			0x44

#define SDMA_PTD_CTRL_PE	0x00000001

#define BESTCOMM_TASKBAR		((volatile UINT32 *) (SDMA_BASE_ADRS + BESTCOMM_TASKBAR_OFF))
#define SDMA_PTD_CTRL		((volatile UINT32 *) (SDMA_BASE_ADRS + SDMA_PTD_CTRL_OFF))
#define BESTCOMM_PTD		((volatile UINT32 *) (SDMA_BASE_ADRS + BESTCOMM_PTD_OFF))
#define BESTCOMM_PEND		((volatile UINT32 *) (SDMA_BASE_ADRS + BESTCOMM_PEND_OFF))
#define BESTCOMM_MASK		((volatile UINT32 *) (SDMA_BASE_ADRS + BESTCOMM_MASK_OFF))
#define BESTCOMM_IPR0		((volatile UINT32 *)(SDMA_BASE_ADRS + BESTCOMM_IPR0_OFF))
#define BESTCOMM_IPR4		((volatile UINT32 *)(SDMA_BASE_ADRS + BESTCOMM_IPR4_OFF))
#define BESTCOMM_IPR8		((volatile UINT32 *)(SDMA_BASE_ADRS + BESTCOMM_IPR8_OFF))
/*-----------------------------------------------------------*/
/* XLB												  0x1F00 */
/*-----------------------------------------------------------*/

#define MBAR_XLB		0x1F00

#define XLB_CR_OFF		0x40 /* arbiter configuration register */
#define XLB_VR_OFF		0x44 /* arbiter version register */
#define XLB_SR_OFF		0x48 /* arbiter status register */
#define XLB_IER_OFF		0x4C /* arbiter interrupt enable register */
#define XLB_ACR_OFF		0x50 /* arbiter address capture register */
#define XLB_BSCR_OFF	0x54 /* arbiter bus signal capture register */
#define XLB_ATTOR_OFF	0x58 /* arbiter addr tenure timeout register */
#define XLB_DTTOR_OFF	0x5C /* arbiter data tenure timeout register */
#define XLB_BATOR_OFF	0x60 /* arbiter bus activity timeout register */
#define XLB_MPER_OFF	0x64 /* arbiter master prio enable register */
#define XLB_MPR_OFF		0x68 /* arbiter master prio register */
#define XLB_BAR_OFF		0x6C /* arbiter base address register */
#define XLB_SWR_OFF		0x70 /* arbiter snoop window register */

#define XLB_BASE_ADRS	(MBAR_VALUE + MBAR_XLB)

#define XLB_CR			((volatile UINT32 *)(XLB_BASE_ADRS + XLB_CR_OFF))
#define XLB_SR			((volatile UINT32 *)(XLB_BASE_ADRS + XLB_SR_OFF))
#define XLB_IER	   		((volatile UINT32 *)(XLB_BASE_ADRS + XLB_IER_OFF))
#define XLB_ACR			((volatile UINT32 *)(XLB_BASE_ADRS + XLB_ACR_OFF))
#define XLB_BSCR		((volatile UINT32 *)(XLB_BASE_ADRS + XLB_BSCR_OFF))
#define XLB_ATTOR		((volatile UINT32 *)(XLB_BASE_ADRS + XLB_ATTOR_OFF))
#define XLB_DTTOR		((volatile UINT32 *)(XLB_BASE_ADRS + XLB_DTTOR_OFF))
#define XLB_BATOR		((volatile UINT32 *)(XLB_BASE_ADRS + XLB_BATOR_OFF))
#define XLB_MPER		((volatile UINT32 *)(XLB_BASE_ADRS + XLB_MPER_OFF))
#define XLB_MPR			((volatile UINT32 *)(XLB_BASE_ADRS + XLB_MPR_OFF))
#define XLB_BAR			((volatile UINT32 *)(XLB_BASE_ADRS + XLB_BAR_OFF))
#define XLB_SWR			((volatile UINT32 *)(XLB_BASE_ADRS + XLB_SWR_OFF))

 
/* arbiter configuration register */

#define XLB_CR_PLDIS_MASK		0x80000000	/* pipeline disabled */
#define XLB_CR_PLDIS_DISABLED	0x80000000
#define XLB_CR_PLDIS_ENABLED	0x00000000
#define XLB_CR_SE_MASK			0x00008000	/* snoop enabled */
#define XLB_CR_SE_DISABLED		0x00000000
#define XLB_CR_SE_ENABLED		0x00008000
#define XLB_CR_USE_WWF_MASK		0x00004000	/* force write-write-flush */
#define XLB_CR_USE_WWF_DISABLED	0x00000000
#define XLB_CR_USE_WWF_ENABLED	0x00004000
#define XLB_CR_TBEN_MASK		0x00002000	/* timebase enable */
#define XLB_CR_TBEN_DISABLED	0x00000000
#define XLB_CR_TBEN_ENABLED		0x00002000
#define XLB_CR_WS_MASK			0x00000800	/* minimum wait state */
#define XLB_CR_WS_0				0x00000000
#define XLB_CR_WS_1				0x00000800
#define XLB_CR_PM_MASK			0x00000060	/* parking mode */
#define XLB_CR_PM_NON			0x00000000
#define XLB_CR_PM_MOST_RECENT	0x00000040
#define XLB_CR_PM_SELECTED		0x00000060
#define XLB_CR_SP_MASK			0x00000700	/* selected parked master */
#define XLB_CR_SP_SHIFT			8
#define XLB_CR_BA_MASK			0x00000008	/* bus activity TO enable */
#define XLB_CR_BA_DISABLED		0x00000000
#define XLB_CR_BA_ENABLED		0x00000008
#define XLB_CR_DT_MASK			0x00000008	/* data tenure TO enable */
#define XLB_CR_DT_DISABLED		0x00000000
#define XLB_CR_DT_ENABLED		0x00000008
#define XLB_CR_AT_MASK			0x00000008	/* address tenure TO enable */
#define XLB_CR_AT_DISABLED		0x00000000
#define XLB_CR_AT_ENABLED		0x00000008

/* arbiter status register */
#define XLB_SR_SEA_MASK			0x00000100	/* slave error ack */
#define XLB_SR_MM_MASK			0x00000080	/* multiple masters */
#define XLB_SR_TTA_MASK			0x00000040	/* TT address only */
#define XLB_SR_TTR_MASK			0x00000020	/* TT reserved */
#define XLB_SR_ECW_MASK			0x00000010	/* external control word R/W */
#define XLB_SR_TTM_MASK			0x00000008	/* TBST/TSIZ mismatch */
#define XLB_SR_BA_MASK			0x00000004	/* bus activity timeout */
#define XLB_SR_DT_MASK			0x00000002	/* data tenure timeout */
#define XLB_SR_AT_MASK			0x00000001	/* address tenure timeout */
#define XLB_SR_CLEAR_ALL		(XLB_SR_ECW_MASK|XLB_SR_DT_MASK|XLB_SR_AT_MASK)

/* arbiter interrupt enable register */
#define XLB_IER_SEAE_MASK		0x00000100	/* slave error ack */
#define XLB_IER_MME_MASK		0x00000080	/* multiple masters */
#define XLB_IER_TTAE_MASK		0x00000040	/* TT address only */
#define XLB_IER_TTRE_MASK		0x00000020	/* TT reserved */
#define XLB_IER_ECWE_MASK		0x00000010	/* external control word R/W */
#define XLB_IER_TTME_MASK		0x00000008	/* TBST/TSIZ mismatch */
#define XLB_IER_BAE_MASK		0x00000004	/* bus activity timeout */
#define XLB_IER_DTE_MASK		0x00000002	/* data tenure timeout */
#define XLB_IER_ATE_MASK		0x00000001	/* address tenure timeout */

/* arbiter bus signal capture register */
#define XLB_BSCR_TSIZ_MASK		0x00000380 	/* captured TSIZ */
#define XLB_BSCR_TSIZ_SHIFT		7
#define XLB_BSCR_GBL_MASK		0x00000040 	/* captured GBL */
#define XLB_BSCR_TBST_MASK		0x00000020 	/* captured TBST */
#define XLB_BSCR_TT_MASK		0x0000001F 	/* captured TT */
#define XLB_BSCR_TT_SHIFT		0

/*-----------------------------------------------------------*/
/* PSC 												  0x2000 */
/* PSC 												  0x2400 */
/* PSC 												  0x2800 */
/*-----------------------------------------------------------*/

/* Offset MBAR to PSCx */
#define MBAR_PSC1			0x2000
#define MBAR_PSC2			0x2200
#define MBAR_PSC3			0x2400
#define MBAR_PSC4			0x2600
#define MBAR_PSC5			0x2800
#define MBAR_PSC6			0x2C00

#define PSC_NUM_MAX			6		/* number of PSC used controllers */
#define PSC_ADRS_OFF		0x200	/* offset between PSC controllers */



#define PSC1_BASE_ADRS		(MBAR_VALUE + MBAR_PSC1)
#define PSC2_BASE_ADRS		(MBAR_VALUE + MBAR_PSC2)
#define PSC3_BASE_ADRS		(MBAR_VALUE + MBAR_PSC3)
#define PSC6_BASE_ADRS		(MBAR_VALUE + MBAR_PSC6)

/* Offset PSCx to register */
#define PSC_MR			0x00  /* byte */
#define PSC_SR_CSR		0x04  /* short */
#define PSC_CR			0x08  /* byte */
#define PSC_RB_TB		0x0c  /* long */
#define PSC_IPCR_ACR	0x10  /* byte */
#define PSC_ISR_IMR		0x14  /* short */
#define PSC_DP			0x18  /* byte */
#define PSC_DL			0x1c  /* byte */
/* IVR */
/* IP */
#define PSC_OP1			0x38  
/* OP0 */
#define PSC_SICR		0x40  
#define PSC_IRCR1		0x44  
#define PSC_IRCR2		0x48  
#define PSC_IRSDR		0x4c  
#define PSC_IRMDR		0x50  
#define PSC_IRFDR		0x54 
#define PSC_RFNUM		0x58  
#define PSC_TFNUM		0x5c  
#define PSC_RFCNTL		0x68  
#define PSC_RFALARM		0x6e  
#define PSC_RFRPTR		0x72  
#define PSC_RFWPTR		0x76  
#define PSC_TFCNTL		0x88  
#define PSC_TFALARM		0x8e  
#define PSC_TFRPTR		0x92  
#define PSC_TFWPTR		0x96  


#define PSC_BASE(num)			((UINT32) (PSC1_BASE_ADRS + (num*PSC_ADRS_OFF)))

#define PSC_MR_ADR(num)			((volatile UINT32 *) (PSC_BASE(num) + PSC_MR))
#define PSC_SR_CSR_ADR(num)		((volatile UINT32 *) (PSC_BASE(num) + PSC_SR_CSR))
#define PSC_CR_ADR(num)			((volatile UINT32 *) (PSC_BASE(num) + PSC_CR))
#define PSC_RB_TB_ADR(num)		((volatile UINT32 *) (PSC_BASE(num) + PSC_RB_TB))
#define PSC_IPCR_ACR_ADR(num)	((volatile UINT32 *) (PSC_BASE(num) + PSC_IPCR_ACR))
#define PSC_ISR_IMR_ADR(num)	((volatile UINT32 *) (PSC_BASE(num) + PSC_ISR_IMR))
#define PSC_DP_ADR(num)			((volatile UINT32 *) (PSC_BASE(num) + PSC_DP))
#define PSC_DL_ADR(num)			((volatile UINT32 *) (PSC_BASE(num) + PSC_DL))
#define PSC_OP1_ADR(num)		((volatile UINT32 *) (PSC_BASE(num) + PSC_OP1))
#define PSC_SICR_ADR(num)		((volatile UINT32 *) (PSC_BASE(num) + PSC_SICR))
#define PSC_IRCR1_ADR(num)		((volatile UINT32 *) (PSC_BASE(num) + PSC_IRCR1))
#define PSC_IRCR2_ADR(num)		((volatile UINT32 *) (PSC_BASE(num) + PSC_IRCR2))
#define PSC_IRSDR_ADR(num)		((volatile UINT32 *) (PSC_BASE(num) + PSC_IRSDR))
#define PSC_IRMDR_ADR(num)		((volatile UINT32 *) (PSC_BASE(num) + PSC_IRMDR))
#define PSC_IRFDR_ADR(num)		((volatile UINT32 *) (PSC_BASE(num) + PSC_IRFDR))
#define PSC_RFNUM_ADR(num)		((volatile UINT32 *) (PSC_BASE(num) + PSC_RFNUM))
#define PSC_TFNUM_ADR(num)		((volatile UINT32 *) (PSC_BASE(num) + PSC_TFNUM))
#define PSC_RFCNTL_ADR(num)		((volatile UINT32 *) (PSC_BASE(num) + PSC_RFCNTL))
#define PSC_RFALARM_ADR(num)	((volatile UINT32 *) (PSC_BASE(num) + PSC_RFALARM))
#define PSC_RFRPTR_ADR(num)		((volatile UINT32 *) (PSC_BASE(num) + PSC_RFRPTR))
#define PSC_RFWPTR_ADR(num)		((volatile UINT32 *) (PSC_BASE(num) + PSC_RFWPTR))
#define PSC_TFCNTL_ADR(num)		((volatile UINT32 *) (PSC_BASE(num) + PSC_TFCNTL))
#define PSC_TFALARM_ADR(num)	((volatile UINT32 *) (PSC_BASE(num) + PSC_TFALARM))
#define PSC_TFRPTR_ADR(num)		((volatile UINT32 *) (PSC_BASE(num) + PSC_TFRPTR))
#define PSC_TFWPTR_ADR(num)		((volatile UINT32 *) (PSC_BASE(num) + PSC_TFWPTR))


/* Interrupt Status and Mask Register */
#define PSC_ISR_IMR_RxRDY  (1<<9)   /* RxRDY or FFULL */
#define PSC_ISR_IMR_TxRDY  (1<<8)   
#define PSC_ISR_IMR_DEOF   (1<<7)   
#define PSC_ISR_IMR_DB     (1<<10)
1234

m5200.h - 源码说明

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