m5200fecend.h

MPC5200 BSP 支持ATA,USB, I2C,扩展网口

#define MOT_FEC_TBD_CRC         0x0400          /* transmit the CRC sequence */
#define MOT_FEC_TBD_DEF         0x0200          /* deferred transmission */
#define MOT_FEC_TBD_HB          0x0100          /* heartbeat error */
#define MOT_FEC_TBD_LC          0x0080          /* late collision */
#define MOT_FEC_TBD_RL          0x0040          /* retransmission limit */
#define MOT_FEC_TBD_UN          0x0002          /* underrun error */
#define MOT_FEC_TBD_CSL         0x0001          /* carrier sense lost */
#define MOT_FEC_TBD_RC_MASK     0x003c          /* retransmission count mask */
 
/* RBD bits definitions */

#define MOT_FEC_RBD_LG          0x00200000          /* frame length violation */
#define MOT_FEC_RBD_NO          0x00100000          /* nonoctet aligned frame */
#define MOT_FEC_RBD_CRC         0x00040000          /* CRC error */
#define MOT_FEC_RBD_OV          0x00020000          /* overrun error */
#define MOT_FEC_RBD_TR          0x00010000          /* truncated frame (>2KB) */
#define MOT_FEC_RBD_ERR         (MOT_FEC_RBD_LG  |                      \
                                 MOT_FEC_RBD_NO  |                      \
                                 MOT_FEC_RBD_CRC |                      \
                                 MOT_FEC_RBD_OV  |                      \
                                 MOT_FEC_RBD_TR)
 
#define MOT_FEC_CRC_POLY	0x04c11db7	/* CRC polynomium: */
						/* x^32 + x^26 + x^23 + */
						/* x^22 + x^16 + x^12 + */
						/* x^11 + x^10 + x^8  + */
						/* x^7  + x^5  + x^4  + */
						/* x^2  + x^1  + x^0  + */

#define MOT_FEC_HASH_MASK	0x7c000000	/* bits 27-31 */
#define MOT_FEC_HASH_SHIFT	0x1a		/* to get the index */
 
/* defines related to the PHY device */

#define MOT_FEC_PHY_PRE_INIT	0x0001		/* PHY info initialized */
#define MOT_FEC_PHY_AUTO	0x0010		/* enable auto-negotiation */
#define MOT_FEC_PHY_TBL		0x0020		/* use negotiation table */
#define MOT_FEC_PHY_100		0x0040		/* PHY may use 100Mbit speed */
#define MOT_FEC_PHY_10		0x0080		/* PHY may use 10Mbit speed */
#define MOT_FEC_PHY_FD		0x0100		/* PHY may use full duplex */
#define MOT_FEC_PHY_HD		0x0200		/* PHY may use half duplex */
#define MOT_FEC_PHY_MAX_WAIT	0x100		/* max delay before */
#define MOT_FEC_PHY_NULL	0xff		/* PHY is not present */
#define MOT_FEC_PHY_DEF		0x0		/* PHY's logical address */

/* allowed PHY's speeds */

#define MOT_FEC_100MBS		100000000       /* bits per sec */
#define MOT_FEC_10MBS		10000000        /* bits per sec */

/*
 * user flags: full duplex mode, loopback mode, serial interface etc.
 * the user may configure some of this options according to his needs 
 * by setting the related bits in the <userFlags> field of the load string.
 */
 
#define MOT_FEC_USR_PHY_NO_AN	0x00000001	/* do not auto-negotiate */
#define MOT_FEC_USR_PHY_TBL	0x00000002	/* use negotiation table */
#define MOT_FEC_USR_PHY_NO_FD	0x00000004	/* do not use full duplex */
#define MOT_FEC_USR_PHY_NO_100	0x00000008	/* do not use 100Mbit speed */
#define MOT_FEC_USR_PHY_NO_HD	0x00000010	/* do not use half duplex */
#define MOT_FEC_USR_PHY_NO_10	0x00000020	/* do not use 10Mbit speed */
#define MOT_FEC_USR_PHY_ISO	0x00000100	/* isolate a PHY */
#define MOT_FEC_USR_SER		0x00000200	/* 7-wire serial interface */
#define MOT_FEC_USR_LOOP	0x00000400	/* loopback mode */
						/* only use it for testing */
#define MOT_FEC_USR_HBC		0x00000080	/* perform heartbeat control */

#define MOT_FEC_TBD_OK		0x1		/* the TBD is a good one */
#define MOT_FEC_TBD_BUSY	0x2		/* the TBD has not been used */
#define MOT_FEC_TBD_ERROR	0x4		/* the TBD is errored */

#define PKT_TYPE_MULTI		0x1	/* packet with a multicast address */
#define PKT_TYPE_UNI		0x2	/* packet with a unicast address */
#define PKT_TYPE_NONE		0x4	/* address type is not meaningful */

#define BUF_TYPE_CL		0x1	/* this's a cluster pointer */
#define BUF_TYPE_MBLK		0x2	/* this's a mblk pointer */

/* frame descriptors definitions */
 
typedef char *			MOT_FEC_BD_ID; 
typedef MOT_FEC_BD_ID	  	MOT_FEC_TBD_ID;
typedef MOT_FEC_BD_ID	  	MOT_FEC_RBD_ID;

/* MII definitions */

#define ETHER_CRC_LEN		0x4	/* CRC length in bytes */
#define MII_MAX_PHY_NUM		0x20	/* max number of attached PHYs */

#define MII_CTRL_REG		0x0	/* Control Register */
#define MII_STAT_REG		0x1	/* Status Register */
#define MII_PHY_ID1_REG		0x2	/* PHY identifier 1 Register */
#define MII_PHY_ID2_REG		0x3	/* PHY identifier 2 Register */
#define MII_AN_ADS_REG		0x4	/* Auto-Negotiation 	  */
					/* Advertisement Register */
#define MII_AN_PRTN_REG		0x5	/* Auto-Negotiation 	    */
					/* partner ability Register */
#define MII_AN_EXP_REG		0x6	/* Auto-Negotiation   */
					/* Expansion Register */
#define MII_AN_NEXT_REG		0x7	/* Auto-Negotiation 	       */
					/* next-page transmit Register */

/* MII control register bit  */

#define MII_CR_COLL_TEST	0x0080		/* collision test */
#define MII_CR_FDX		0x0100		/* FDX =1, half duplex =0 */
#define MII_CR_RESTART		0x0200		/* restart auto negotiation */
#define MII_CR_ISOLATE		0x0400		/* isolate PHY from MII */
#define MII_CR_POWER_DOWN	0x0800		/* power down */
#define MII_CR_AUTO_EN		0x1000		/* auto-negotiation enable */
#define MII_CR_100		0x2000		/* 0 = 10mb, 1 = 100mb */
#define MII_CR_LOOPBACK		0x4000		/* 0 = normal, 1 = loopback */
#define MII_CR_RESET		0x8000		/* 0 = normal, 1 = PHY reset */
#define MII_CR_NORM_EN		0x0000		/* just enable the PHY */

/* MII Status register bit definitions */

#define MII_SR_LINK_STATUS	0x0004       	/* link Status -- 1 = link */
#define MII_SR_AUTO_SEL		0x0008       	/* auto speed select capable */
#define MII_SR_REMOTE_FAULT     0x0010      	/* Remote fault detect */
#define MII_SR_AUTO_NEG         0x0020      	/* auto negotiation complete */
#define MII_SR_10T_HALF_DPX     0x0800     	/* 10BaseT HD capable */
#define MII_SR_10T_FULL_DPX     0x1000    	/* 10BaseT FD capable */
#define MII_SR_TX_HALF_DPX      0x2000    	/* TX HD capable */
#define MII_SR_TX_FULL_DPX      0x4000     	/* TX FD capable */
#define MII_SR_T4               0x8000    	/* T4 capable */

/* MII Link Code word  bit definitions */

#define MII_BP_FAULT	0x2000       	/* remote fault */
#define MII_BP_ACK	0x4000       	/* acknowledge */
#define MII_BP_NP	0x8000       	/* nexp page is supported */

/* MII Next Page bit definitions */

#define MII_NP_TOGGLE	0x0800       	/* toggle bit */
#define MII_NP_ACK2	0x1000       	/* acknowledge two */
#define MII_NP_MSG	0x2000       	/* message page */
#define MII_NP_ACK1	0x4000       	/* acknowledge one */
#define MII_NP_NP	0x8000       	/* nexp page will follow */

/* MII Expansion Register bit definitions */

#define MII_EXP_FAULT	0x0010       	/* parallel detection fault */
#define MII_EXP_PRTN_NP	0x0008       	/* link partner next-page able */
#define MII_EXP_LOC_NP	0x0004       	/* local PHY next-page able */
#define MII_EXP_PR	0x0002       	/* full page received */
#define MII_EXP_PRT_AN	0x0001       	/* link partner auto negotiation able */

/* technology ability field bit definitions */

#define MII_TECH_10BASE_T	0x0020	/* 10Base-T */
#define MII_TECH_10BASE_FD	0x0040	/* 10Base-T Full Duplex */
#define MII_TECH_100BASE_TX	0x0080	/* 100Base-TX */
#define MII_TECH_100BASE_TX_FD	0x0100	/* 100Base-TX Full Duplex */
#define MII_TECH_100BASE_T4	0x0200	/* 100Base-T4 */
#define MII_TECH_MASK		0x1fe0	/* technology abilities mask */

#define MII_AN_FAIL		0x10	/* auto-negotiation fail */
#define MII_STAT_FAIL		0x20	/* errors in the status register */
#define MOT_FEC_PHY_NO_ABLE	0x40	/* the PHY lacks some abilities */


/* base address of SRAM area to store parameters used by Ethernet tasks */
#define FEC_PARAM_BASE		(MBAR_SRAM + 0x0800)

/* base address of SRAM area for buffer descriptors */
#define FEC_BD_BASE		(MBAR_SRAM + 0x0820)

/*
 * this table may be customized by the user in configNet.h
 */
 
IMPORT INT16 m5200FecPhyAnOrderTbl [];

/* 
 * the table below is used to translate user settings 
 * into MII-standard values for technology abilities.
 */

LOCAL UINT16 miiAnLookupTbl [] = {
				  MII_TECH_10BASE_T,	
				  MII_TECH_10BASE_FD,
				  MII_TECH_100BASE_TX,
				  MII_TECH_100BASE_TX_FD,
				  MII_TECH_100BASE_T4	
			         };

LOCAL UINT16 miiCrLookupTbl [] = {
				  MII_CR_NORM_EN,	
				  MII_CR_FDX,
				  MII_CR_100,
				  (MII_CR_100 | MII_CR_FDX),
				  (MII_CR_100 | MII_CR_FDX)	
			         };

typedef struct mii_regs
    {
    UINT16		phyStatus;	/* PHY's status register */
    UINT16		phyCtrl;	/* PHY's control register */
    UINT16		phyId1;		/* PHY's identifier field 1 */
    UINT16		phyId2;		/* PHY's identifier field 2 */
    UINT16		phyAds;		/* PHY's advertisement register */
    UINT16		phyPrtn;	/* PHY's partner register */
    UINT16		phyExp;		/* PHY's expansion register */
    UINT16		phyNext;	/* PHY's next paget transmit register */
    } MII_REGS;
 
typedef struct phy_info
    {
    MII_REGS		miiRegs;	/* PHY registers */
    UINT8		phyAddr;	/* address of the PHY to be used */
    UINT8		isoPhyAddr;	/* address of a PHY to isolate */
    UINT32		phyFlags;	/* some flags */
    UINT32              phySpeed;     	/* 10/100 Mbit/sec */
    UINT32              phyMode;     	/* half/full duplex mode */
    UINT32              phyDefMode;    	/* default operating mode */
    } PHY_INFO;

typedef struct mot_fec_tbd_list
    {
    UINT16			fragNum;
    UINT16			pktType;
    UCHAR *			pBuf;
    UINT16			bufType;
    struct mot_fec_tbd_list *	pNext;
    MOT_FEC_TBD_ID		pTbd;
    } MOT_FEC_TBD_LIST;

typedef MOT_FEC_TBD_LIST *	MOT_FEC_TBD_LIST_ID; 

/* The definition of the driver control structure */
 
typedef struct drv_ctrl
    {
    END_OBJ             endObj;         /* base class */
    int                 unit;           /* unit number */
    UINT32              MBARAddr;     	/* internal RAM base address */
    int                 ivec;           /* interrupt vector number */
    int                 ilevel;         /* interrupt level */
    UINT32              fifoTxBase;     /* address of Tx FIFO in internal RAM */
    UINT32              fifoRxBase;     /* address of Rx FIFO in internal RAM */
    char *              pBufBase;       /* FEC memory pool base */
    ULONG               bufSize;        /* FEC memory pool size */
    UINT16              rbdNum;         /* number of RBDs */
    MOT_FEC_RBD_ID			rbdBase;        /* RBD ring */
    UINT16              rbdIndex;       /* RBD index */
    UINT16              tbdNum;         /* number of TBDs */
    MOT_FEC_TBD_ID      tbdBase;        /* TBD ring */
    UINT16              tbdIndex;       /* TBD index */
    UINT16              usedTbdIndex;   /* used TBD index */
    UINT16              cleanTbdNum;    /* number of clean TBDs */
    BOOL                txStall;        /* tx handler stalled - no Tbd */
    MOT_FEC_TBD_LIST * 	pTbdList [MOT_FEC_TBD_MAX];
 
					/* list of TBDs */
    ULONG               userFlags;      /* some user flags */
    INT8                flags;          /* driver state */
    BOOL                loaded;         /* interface has been loaded */
    BOOL                intrConnect;    /* interrupt has been connected */
    UINT32		intMask;	/* interrupt mask register */
    UCHAR *		pTxPollBuf;	/* cluster pointer for poll mode */
    UCHAR *            	rxBuf[MOT_FEC_RBD_MAX];
    
                                            /* array of pointers to clusters */
    SEM_ID		miiSem;		/* synch semaphore for mii frames */
    SEM_ID		graSem;		/* synch semaphore for graceful */
					/* transmit command */
    char *              pClBlkArea;     /* cluster block pointer */
    UINT32              clBlkSize;     	/* clusters block memory size */
    char *              pMBlkArea;     	/* mBlock area pointer */
    UINT32              mBlkSize;     	/* mBlocks area memory size */
    CACHE_FUNCS         bdCacheFuncs;   /* cache descriptor */
    CACHE_FUNCS         bufCacheFuncs;  /* cache descriptor */
    CL_POOL_ID          pClPoolId;      /* cluster pool identifier */
    PHY_INFO		*phyInfo;	/* info on a MII-compliant PHY */
    UINT                RevD;           /* whether the 860 being used is revd*/
    } DRV_CTRL;

/* 
 * this cache functions descriptors is used to flush/invalidate
 * the FEC's data buffers. They are set to the system's cache
 * flush and invalidate routine. This will allow proper operation
 * of the driver if data cache are turned on.
 */

IMPORT STATUS   cacheArchInvalidate (CACHE_TYPE, void *, size_t);
 
IMPORT STATUS   cacheArchFlush (CACHE_TYPE, void *, size_t);
 
LOCAL   CACHE_FUNCS     motFecBufCacheFuncs;
LOCAL	FUNCPTR motFecBufInvRtn = cacheArchInvalidate;
LOCAL	FUNCPTR motFecBufFlushRtn = cacheArchFlush;

IMPORT STATUS	sysFecEnetAddrGet (UINT32 motCmpAddr, UCHAR * address);
IMPORT FUNCPTR  _func_motFecPhyInit;
IMPORT FUNCPTR  _func_motFecHbFail;

#ifdef __cplusplus
}
#endif

#endif /* __INCmotFecEndh */