m5200fecend.h

MPC5200 BSP 支持ATA,USB, I2C,扩展网口

/* m5200FecEnd.h - Motorola FEC Ethernet network interface header */

/* Copyright 1990-1998 Wind River Systems, Inc. */
/*
modification history
--------------------
01b,09feb99,cn	changes required by performance improvement (SPR# 24883).
01a,09nov98,cn	written.
*/

#ifndef __INCm5200FecEndh
#define __INCm5200FecEndh

/* includes */

#ifdef __cplusplus
extern "C" {
#endif
 
#include "etherLib.h"
#include "capi/mgt5200/mgt5200.h"

/* defines */

/*
 * redefine the macro below in the bsp if you need to access the device
 * registers/descriptors in a more suitable way.
 */

#ifndef MOT_FEC_LONG_WR
#define MOT_FEC_LONG_WR(addr, value)                                        \
    (* (addr) = ((UINT32) (value)))
#endif /* MOT_FEC_LONG_WR */
 
#ifndef MOT_FEC_WORD_WR
#define MOT_FEC_WORD_WR(addr, value)                                        \
    (* (addr) = ((UINT16) (value)))
#endif /* MOT_FEC_WORD_WR */
 
#ifndef MOT_FEC_BYTE_WR
#define MOT_FEC_BYTE_WR(addr, value)                                        \
    (* (addr) = ((UINT8) (value)))
#endif /* MOT_FEC_BYTE_WR */
 
#ifndef MOT_FEC_LONG_RD
#define MOT_FEC_LONG_RD(addr, value)                                        \
    ((value) = (* (UINT32 *) (addr)))
#endif /* MOT_FEC_LONG_RD */
 
#ifndef MOT_FEC_WORD_RD
#define MOT_FEC_WORD_RD(addr, value)                                        \
    ((value) = (* (UINT16 *) (addr)))
#endif /* MOT_FEC_WORD_RD */
 
#ifndef MOT_FEC_BYTE_RD
#define MOT_FEC_BYTE_RD(addr, value)                                        \
    ((value) = (* (UINT8 *) (addr)))
#endif /* MOT_FEC_BYTE_RD */
 
/*
 * Default macro definitions for BSP interface.
 * These macros can be redefined in a wrapper file, to generate
 * a new module with an optimized interface.
 */
 
#ifndef SYS_FEC_INT_CONNECT
#define SYS_FEC_INT_CONNECT(pDrvCtrl, pFunc, arg, ret)                      \
{                                                                           \
IMPORT STATUS intConnect (VOIDFUNCPTR *, VOIDFUNCPTR, int);		    \
ret = OK;                                                                   \
                                                                            \
if (MOT_FEC_VECTOR (pDrvCtrl) && (!(pDrvCtrl->intrConnect)))  		    \
    {                                                                       \
    pDrvCtrl->intrConnect = TRUE;                                   	    \
    ret = (intConnect) ((VOIDFUNCPTR*)                              	    \
                                INUM_TO_IVEC (MOT_FEC_VECTOR (pDrvCtrl)),   \
                                (pFunc), (int) (arg));                      \
    }                                                                       \
}
#endif /* SYS_FEC_INT_CONNECT */
 
#ifndef SYS_FEC_INT_DISCONNECT
#define SYS_FEC_INT_DISCONNECT(pDrvCtrl, pFunc, arg, ret)                   \
{                                                                           \
ret = OK;                                                                   \
                                                                            \
if (MOT_FEC_VECTOR (pDrvCtrl) )             	    \
    {                                                                       \
    pDrvCtrl->intrConnect = FALSE;                                          \
    }                                                                       \
}
#endif /* SYS_FEC_INT_DISCONNECT */
 
#ifndef SYS_FEC_INT_ENABLE
#define SYS_FEC_INT_ENABLE(pDrvCtrl, ret)				    \
{                                                                           \
IMPORT int intEnable (int);						    \
ret = OK;                                                                   \
                                                                            \
if (MOT_FEC_VECTOR (pDrvCtrl)) 			    			    \
    ret = intEnable ((int) (MOT_FEC_VECTOR (pDrvCtrl)));		    \
}
#endif /* SYS_FEC_INT_ENABLE */
 
#ifndef SYS_FEC_INT_DISABLE
#define SYS_FEC_INT_DISABLE(pDrvCtrl, ret)				    \
{                                                                           \
IMPORT int intDisable (int);						    \
ret = OK;                                                                   \
                                                                            \
if (MOT_FEC_VECTOR (pDrvCtrl)) 			    			    \
    ret = intDisable ((int) (MOT_FEC_VECTOR (pDrvCtrl)));		    \
}
#endif /* SYS_FEC_INT_DISABLE */
 
#define SYS_FEC_ENET_ADDR_GET(address)                                  \
if (sysFecEnetAddrGet != NULL)                                          \
    if (sysFecEnetAddrGet (pDrvCtrl->MBARAddr, (address)) == ERROR)   \
        {                                                               \
        errnoSet (S_iosLib_INVALID_ETHERNET_ADDRESS);                   \
        return (NULL);                                                  \
        }
 
#define MOT_FEC_DEV_NAME       	"motfec"
#define MOT_FEC_DEV_NAME_LEN   	7
#define MOT_FEC_TBD_DEF_NUM    	64		/* default number of TBDs */
#define MOT_FEC_RBD_DEF_NUM    	48		/* default number of RBDs */
#define MOT_FEC_TX_CL_NUM    	128		/* number of tx clusters */
#define MOT_FEC_BD_LOAN_NUM    	256		/* loaned BDs */
#define MOT_FEC_TBD_MAX         128     	/* max number of TBDs */
#define MOT_FEC_RBD_MAX         128     	/* max number of TBDs */
#define MOT_FEC_WAIT_MAX	0xf0000000	/* max delay after sending */

#define MOT_FEC_ADDR_LEN        6               /* ethernet address length */

/* Control/Status Registers (CSR) definitions */
 
#define MOT_FEC_CSR_OFF         0x3000  /* CSRs offset in the MPC5200 RAM */
#define MOT_FEC_ID_OFF      		0x3000  /* FEC ID register */
#define MOT_FEC_EVENT_OFF       0x3004  /* interrupt event register */
#define MOT_FEC_MASK_OFF        0x3008  /* interrupt mask register */
#define MOT_FEC_RX_ACT_OFF      0x3010  /* rx ring has been updated */
#define MOT_FEC_TX_ACT_OFF      0x3014  /* tx ring has been updated */
#define MOT_FEC_CTRL_OFF        0x3024  /* FEC control register */
#define MOT_FEC_MII_DATA_OFF    0x3040  /* MII data register */
#define MOT_FEC_MII_SPEED_OFF   0x3044  /* MII speed register */
#define MOT_FEC_MIB_CTRL_OFF   	0x3064  /* MIB control register */
#define MOT_FEC_RX_CTRL_OFF     0x3084  /* rx control register */
#define MOT_FEC_HASH_INFO_OFF   0x3088  /* fec rx hash information register*/
#define MOT_FEC_TX_CTRL_OFF     0x30c4  /* tx control register */
#define MOT_FEC_ADDR_L_OFF      0x30e4  /* lower 32-bits of MAC address */
#define MOT_FEC_ADDR_H_OFF      0x30e8  /* upper 16-bits of MAC address */
#define MOT_FEC_PAUSE_OFF       0x30ec  /* fec op/pause duration register */
#define MOT_FEC_INVD_ADDR1_OFF  0x3118  /* fec descriptor individual Address 1 register */
#define MOT_FEC_INVD_ADDR2_OFF  0x311C  /* fec descriptor individual Address 2 register */
#define MOT_FEC_HASH_H_OFF      0x3120  /* upper 32-bits of hash table */
#define MOT_FEC_HASH_L_OFF      0x3124  /* lower 32-bits of hash table */
#define MOT_FEC_TXFIFO_WMRK_OFF 0x3144  /* tx fifo watermark register */
#define MOT_FEC_RXFIFO_DATA_OFF 0x3184
#define MOT_FEC_RXFIFO_STAT_OFF 0x3188
#define MOT_FEC_RXFIFO_CTRL_OFF 0x318C
#define MOT_FEC_RECV_RFRAME_OFF 0x3190
#define MOT_FEC_RECV_WFRAME_OFF 0x3194
#define MOT_FEC_RECV_ALARM_OFF  0x3198
#define MOT_FEC_RXFIFO_RPOINTER_OFF 0x319C
#define MOT_FEC_RXFIFO_WPOINTER_OFF 0x31A0
#define MOT_FEC_TXFIFO_DATA_OFF 0x31A4
#define MOT_FEC_TXFIFO_STAT_OFF 0x31A8
#define MOT_FEC_TXFIFO_CTRL_OFF 0x31AC
#define MOT_FEC_TRANS_RFRAME_OFF 0x31B0
#define MOT_FEC_TRANS_WFRAME_OFF 0x31B4
#define MOT_FEC_TRANS_ALARM_OFF  0x31B8
#define MOT_FEC_TXFIFO_RPOINTER_OFF 0x31BC
#define MOT_FEC_TXFIFO_WPOINTER_OFF 0x31C0
#define MOT_FEC_RESET_OFF				 0x31C4
#define MOT_FEC_XF_FSM_OFF			0x31C8

/* Ethernet CSR bit definitions */
 
#define MOT_FEC_ETH_EN          0x00000002      /* enable Ethernet operation */
#define MOT_FEC_ETH_DIS         0x00000000      /* disable Ethernet operation */
#define MOT_FEC_ETH_RES         0x00000001      /* reset the FEC */
#define MOT_FEC_ETH_FOE					0x00000004
#define MOT_FEC_CTRL_MASK_REVD  0x00000007      /* FEC control register mask */
#define MOT_FEC_CTRL_MASK       0x00000003      /* FEC control register mask */
 
/*
 * interrupt bits definitions: these are common to both the
 * mask and the event register.
 */
 
#define MOT_FEC_EVENT_HB        0x80000000      /* heartbeat error */
#define MOT_FEC_EVENT_BABR      0x40000000      /* babbling rx error */
#define MOT_FEC_EVENT_BABT      0x20000000      /* babbling tx error */
#define MOT_FEC_EVENT_GRA       0x10000000      /* graceful stop complete */
#define MOT_FEC_EVENT_TXF       0x08000000      /* tx frame */
#define MOT_FEC_EVENT_MII       0x00800000      /* MII transfer */
#define MOT_FEC_EVENT_LAT_COL   0x00200000      /* late collison */
#define MOT_FEC_EVENT_COL_RETRY 0x00100000      /* collison retry limit */
#define MOT_FEC_EVENT_XFIFO_UN  0x00080000      /* transmit fifo underrun */
#define MOT_FEC_EVENT_XFIFO_ERR 0x00040000      /* transmit fifo error */
#define MOT_FEC_EVENT_RFIFO_ERR 0x00020000      /* receive fifo error */


#define MOT_FEC_EVENT_MSK       0xf8be0000      /* clear all interrupts */
#define MOT_FEC_MASK_ALL        MOT_FEC_EVENT_MSK    /* mask all interrupts */
 
/* transmit and receive active registers definitions */
 
#define MOT_FEC_TX_ACT          0x01000000      /* tx active bit */
#define MOT_FEC_RX_ACT          0x01000000      /* rx active bit */

/* * Bit fields for FEC transmit finite state machine. */
/*							0xfc000000	reserved						*/
#define MOT_FEC_FSM_CRC			0x02000000	/* append CRC (typical use)		*/
#define MOT_FEC_FSM_ENFSM		0x01000000	/* enable CRC FSM (typical use)	*/
/*							0x00ffffff	reserved						*/
 
/* MII management frame CSRs */
 
#define MOT_FEC_MII_ST          0x40000000      /* start of frame delimiter */
#define MOT_FEC_MII_OP_RD       0x20000000      /* perform a read operation */
#define MOT_FEC_MII_OP_WR       0x10000000      /* perform a write operation */
#define MOT_FEC_MII_ADDR_MSK    0x0f800000      /* PHY address field mask */
#define MOT_FEC_MII_REG_MSK     0x007c0000      /* PHY register field mask */
#define MOT_FEC_MII_TA          0x00020000      /* turnaround */
#define MOT_FEC_MII_DATA_MSK    0x0000ffff      /* PHY data field */
#define MOT_FEC_MII_RA_SHIFT    0x12            /* mii reg address bits */
#define MOT_FEC_MII_PA_SHIFT    0x17            /* mii PHY address bits */
 
#define MOT_FEC_MII_PRE_DIS     0x00000080      /* desable preamble */
#define MOT_FEC_MII_SPEED_33    0x0000000e      /* recommended for 33Mhz IPB CLK */
#define MOT_FEC_MII_SPEED_66    0x0000001c      /* recommended for 66Mhz IPB CLK */
#define MOT_FEC_MII_SPEED_132   0x00000038      /* recommended for 132Mhz IPB CLK */
#define MOT_FEC_MII_MAN_DIS     0x00000000      /* disable the MII management */
                                                /* interface */
#define MOT_FEC_MII_SPEED_MSK   0xffffff81      /* speed field mask */
 
/* receive control/hash registers bit definitions */

#define MOT_FEC_RX_CTRL_FCE     0x00000020      /* flow control enable */
#define MOT_FEC_RX_CTRL_BCREJ   0x00000010      /* broadcast reject */ 
#define MOT_FEC_RX_CTRL_PROM    0x00000008      /* promiscous mode */
#define MOT_FEC_RX_CTRL_MII     0x00000004      /* select MII interface */
#define MOT_FEC_RX_CTRL_DRT     0x00000002      /* disable rx on transmit */
#define MOT_FEC_RX_CTRL_LOOP    0x00000001      /* loopback mode */
#define MOT_FEC_RX_FR_MSK       0x07ff0000      /* rx frame length mask */
#define MOT_FEC_RCNTRL_MAX_FL_SHIFT	16

/* rx FIFO control registers bit definitions */
#define MOT_FEC_FIFO_CNTRL_FRAME 0x08000000			
#define MOT_FEC_FIFO_CNTRL_GR_SHIFT	24


/*
 * Bit fields for FEC transmit FIFO watermark, x_wmrk above.
 */
#define FEC_XWMRK_64		0x00000000	/*   64 bytes written to TxFIFO	*/
#define FEC_XWMRK_128		0x00000001	/*  128 bytes written to TxFIFO	*/
#define FEC_XWMRK_192		0x00000002	/*  192 bytes written to TxFIFO	*/
#define FEC_XWMRK_256		0x00000003	/*  256 bytes written to TxFIFO	*/
#define FEC_XWMRK_320		0x00000004	/*  320 bytes written to TxFIFO	*/
#define FEC_XWMRK_384		0x00000005	/*  384 bytes written to TxFIFO	*/
#define FEC_XWMRK_448		0x00000006	/*  448 bytes written to TxFIFO	*/
#define FEC_XWMRK_512		0x00000007	/*  512 bytes written to TxFIFO	*/
#define FEC_XWMRK_576		0x00000008	/*  576 bytes written to TxFIFO	*/
#define FEC_XWMRK_640		0x00000009	/*  640 bytes written to TxFIFO	*/
#define FEC_XWMRK_704		0x0000000a	/*  704 bytes written to TxFIFO	*/
#define FEC_XWMRK_768		0x0000000b	/*  768 bytes written to TxFIFO	*/
#define FEC_XWMRK_832		0x0000000c	/*  832 bytes written to TxFIFO	*/
#define FEC_XWMRK_896		0x0000000d	/*  896 bytes written to TxFIFO	*/
#define FEC_XWMRK_960		0x0000000e	/*  960 bytes written to TxFIFO	*/
#define FEC_XWMRK_1024		0x0000000f	/* 1024 bytes written to TxFIFO	*/

 
/* transmit control register bit definitions */
#define MOT_FEC_TX_CTRL_RFC     0x00000010      /* read only pause frame received */
#define MOT_FEC_TX_CTRL_TFC     0x00000008      /* transmit pause frame */ 
#define MOT_FEC_TX_CTRL_FD      0x00000004      /* enable full duplex mode */
#define MOT_FEC_TX_CTRL_HBC     0x00000002      /* HB check is performed */
#define MOT_FEC_TX_CTRL_GRA     0x00000001      /* issue a graceful tx stop */
 
/* rx/tx buffer descriptors definitions */
 
#define MOT_FEC_RBD_SZ          8       /* RBD size in byte */
#define MOT_FEC_TBD_SZ          8       /* TBD size in byte */
#define MOT_FEC_TBD_MIN         6       /* min number of TBDs */
#define MOT_FEC_RBD_MIN         4       /* min number of RBDs */
#define MOT_FEC_TBD_POLL_NUM    1       /* one TBD for poll operation */
#define CL_OVERHEAD             4       /* prepended cluster overhead */
#define CL_ALIGNMENT            4       /* cluster required alignment */
#define MBLK_ALIGNMENT          4       /* mBlks required alignment */
#define MOT_FEC_BD_ALIGN        0x10    /* required alignment for RBDs */
/* 1500+14+4=1518*/
#define MOT_FEC_MAX_PCK_SZ      (ETHERMTU + SIZEOF_ETHERHEADER          \
                                 + ETHER_CRC_LEN)
 
#define MOT_FEC_BD_STAT_OFF     0       /* offset of the status word */
#define MOT_FEC_BD_LEN_OFF      2       /* offset of the data length word */
#define MOT_FEC_BD_ADDR_OFF     4       /* offset of the data pointer word */
 
/* TBD bits definitions */
 
#define MOT_FEC_TBD_RDY         0x4000          /* ready for transmission */
#define MOT_FEC_TBD_WRAP        0x2000          /* look at CSR5 for next bd */
#define MOT_FEC_TBD_INT         0x1000          /* transmit interrupt */
#define MOT_FEC_TBD_LAST        0x0800          /* last bd in this frame */