syspci.c

MPC5200 BSP 支持ATA,USB, I2C,扩展网口

	  *PCIRFSR = 0x007f0000;
    
    /* clear pending errors, mask interrupts, deassert reset */
  
    *PCIARB = PCIARB_RESET; /* reset arbiter */
    for (i=0; i<100000;i++) ;
    *PCIARB = 0;
	        
    /* disable config space IO */

    *PCICAR = 0;
		   
		/* reset PCI*/
		*PCIGSCR |= 1;
		for (i=0; i<100000;i++) ;
		*PCIGSCR &= ~1;

    retVal = pciConfigLibInit (PCI_MECHANISM_0, 
		               (ULONG) sysPciConfigRead,
                               (ULONG) sysPciConfigWrite,
                               (ULONG) sysPciSpecialCycle);
    return retVal;
    }

void pciCtlInt()
{
    UINT32 status1 = *PCIGSCR;
    UINT32 status2 = *PCIISR;
     *PCIGSCR |= status1; /* clear events */
    *PCIISR |= status2; /* clear events */

    if ((status1 & PCIGSCR_BM) != 0)
    {
		/* Broken master detected */
				#ifdef	PCI_DEBUG
        logMsg ("PCI XLB Error: broken master detected\n",1,2,3,4,5,6);
				#endif
    }

    if ((status1 & PCIGSCR_PE) != 0)
    {
	/* Parity error detected */
				#ifdef	PCI_DEBUG
        logMsg ("PCI XLB Error: parity error\n",1,2,3,4,5,6);
				#endif
    }

    if ((status1 & PCIGSCR_SE) != 0)
    {
	/* System error detected */
				#ifdef	PCI_DEBUG
        logMsg ("PCI XLB Error: system error\n",1,2,3,4,5,6);
				#endif
    }

    if ((status2 & PCIISR_RE) != 0)
    {
	/* Retry error */
				#ifdef	PCI_DEBUG
        logMsg ("PCI XLB Error: retry count exceeded\n",1,2,3,4,5,6);
				#endif
    }

    if ((status2 & PCIISR_IA) != 0)
    {
	/* Initiator abort */
				#ifdef	PCI_DEBUG
        logMsg ("PCI XLB Error: initiator aborted due to timeout\n",1,2,3,4,5,6);
				#endif
    }
    
    if ((status2 & PCIISR_TA) != 0)
    {
	/* Target abort */
				#ifdef	PCI_DEBUG
        logMsg ("PCI XLB Error: target abort\n",1,2,3,4,5,6);
        #endif
    }
}
void pciRxInt()
{
    UINT32 status3 = *PCIRSR;
    UINT32 status4 = *PCIRFSR;
    
    *PCIRSR |= status3; /* clear events */ 
    *PCIRFSR |= status4; /* clear events */
    if ((status3 & 0x01000000) != 0)
    {
    			#ifdef	PCI_DEBUG
    		  logMsg ("PCI RX COMMBUS : packets terminates normally\n",1,2,3,4,5,6); 
    		  #endif
    }
    if ((status3 & 0x00800000) != 0)
    {
    			 #ifdef	PCI_DEBUG
    		   logMsg ("PCI RX COMMBUS : bus error type3\n",1,2,3,4,5,6);
    		   #endif
    }
    if ((status3 & 0x00400000) != 0)
    {
    			 #ifdef	PCI_DEBUG
    		   logMsg ("PCI RX COMMBUS : bus error type2\n",1,2,3,4,5,6);
    		   #endif
    }
    if ((status3 & 0x00200000) != 0)
    {
    			 #ifdef	PCI_DEBUG
    		   logMsg ("PCI RX COMMBUS : bus error type1\n",1,2,3,4,5,6);
    		   #endif
    }
    if ((status3 & 0x00100000) != 0)
    {
    			 #ifdef	PCI_DEBUG
    		   logMsg ("PCI RX COMMBUS : FIFO error\n",1,2,3,4,5,6);
    		   #endif
    		   if ((status4 & 0x00400000) != 0)
    				{
    						#ifdef	PCI_DEBUG
    		   			logMsg ("RX FIFO error : RXW error\n",1,2,3,4,5,6);
    		   			#endif
    		   
    				}
    				if ((status4 & 0x00200000) != 0)
    				{
    						#ifdef	PCI_DEBUG
    		   			logMsg ("RX FIFO error : underflow error\n",1,2,3,4,5,6);
    		   			#endif
    				}
    				if ((status4 & 0x00100000) != 0)
    				{
    						#ifdef	PCI_DEBUG
    		   			logMsg ("RX FIFO error : overflow error\n",1,2,3,4,5,6);
    		   			#endif
    				}
    				if ((status4 & 0x00080000) != 0)
    				{
    						#ifdef	PCI_DEBUG
    		   			logMsg ("RX FIFO error : Frame Ready\n",1,2,3,4,5,6);
    		   			#endif
    				}
    				if ((status4 & 0x00040000) != 0)
    				{
    						#ifdef	PCI_DEBUG
    		   			logMsg ("RX FIFO error : FIFO FULL\n",1,2,3,4,5,6);
    		   			#endif
    				}
						if ((status4 & 0x00020000) != 0)
    				{
    						#ifdef	PCI_DEBUG
    		   			logMsg ("RX FIFO error : FIFO Alarm\n",1,2,3,4,5,6);
    		   			#endif
    				}   
    				if ((status4 & 0x00010000) != 0)
    				{
    						#ifdef	PCI_DEBUG
    		   			logMsg ("RX FIFO error : FIFO Empty\n",1,2,3,4,5,6);
    		   			#endif
    				}    	 				
    		   
    }
    if ((status3 & 0x00080000) != 0)
    {
    			#ifdef	PCI_DEBUG
    		   logMsg ("PCI RX COMMBUS : system error \n",1,2,3,4,5,6);
    		   /* reset rx controller */
    			 *PCIRER |=0x80000000;
    			 volatile int i;
    			 for (i=0; i<100*4; i++) {};
     			 *PCIRER &=0x7FFFFFFF;
    		  #endif
    }
    if ((status3 & 0x00040000) != 0)
    {
    			#ifdef	PCI_DEBUG
    		   logMsg ("PCI RX COMMBUS : retry error \n",1,2,3,4,5,6);
    		  #endif
    }
    if ((status3 & 0x00020000) != 0)
    {
    			#ifdef	PCI_DEBUG
    		   logMsg ("PCI RX COMMBUS : target abort\n",1,2,3,4,5,6);
    		  #endif
    }
    if ((status3 & 0x00010000) != 0)
    {
    			#ifdef	PCI_DEBUG
    		   logMsg ("PCI RX COMMBUS : initiator abort\n",1,2,3,4,5,6);
    		  #endif
    }
    
}
void pciTxInt()
{
    UINT32 status3 = *PCITSR;
    UINT32 status4 = *PCITFSR;
    *PCITSR |= status3; /* clear events */ 
    *PCITFSR |= status4; /* clear events */
    if ((status3 & 0x01000000) != 0)
    {
    			#ifdef	PCI_DEBUG
    		  logMsg ("PCI TX COMMBUS : packets terminates normally\n",1,2,3,4,5,6); 
    		  #endif
    }
    if ((status3 & 0x00800000) != 0)
    {
    			 #ifdef	PCI_DEBUG
    		   logMsg ("PCI TX COMMBUS : bus error type3\n",1,2,3,4,5,6);
    		   #endif
    }
    if ((status3 & 0x00400000) != 0)
    {
    			 #ifdef	PCI_DEBUG
    		   logMsg ("PCI TX COMMBUS : bus error type2\n",1,2,3,4,5,6);
    		   #endif
    }
    if ((status3 & 0x00200000) != 0)
    {
    			 #ifdef	PCI_DEBUG
    		   logMsg ("PCI TX COMMBUS : bus error type1\n",1,2,3,4,5,6);
    		   #endif
    }
    if ((status3 & 0x00100000) != 0)
    {
    			 #ifdef	PCI_DEBUG
    		   logMsg ("PCI TX COMMBUS : FIFO error\n",1,2,3,4,5,6);
    		   #endif
    		   if ((status4 & 0x00400000) != 0)
    				{
    						#ifdef	PCI_DEBUG
    		   			logMsg ("TX FIFO error : RXW error\n",1,2,3,4,5,6);
    		   			#endif
    		   
    				}
    				if ((status4 & 0x00200000) != 0)
    				{
    						#ifdef	PCI_DEBUG
    		   			logMsg ("TX FIFO error : underflow error\n",1,2,3,4,5,6);
    		   			#endif
    				}
    				if ((status4 & 0x00100000) != 0)
    				{
    						#ifdef	PCI_DEBUG
    		   			logMsg ("TX FIFO error : overflow error\n",1,2,3,4,5,6);
    		   			#endif
    				}
    				if ((status4 & 0x00080000) != 0)
    				{
    						#ifdef	PCI_DEBUG
    		   			logMsg ("TX FIFO error : Frame Ready\n",1,2,3,4,5,6);
    		   			#endif
    				}
    				if ((status4 & 0x00040000) != 0)
    				{
    						#ifdef	PCI_DEBUG
    		   			logMsg ("TX FIFO error : FIFO FULL\n",1,2,3,4,5,6);
    		   			#endif
    				}
						if ((status4 & 0x00020000) != 0)
    				{
    						#ifdef	PCI_DEBUG
    		   			logMsg ("TX FIFO error : FIFO Alarm\n",1,2,3,4,5,6);
    		   			#endif
    				}   
    				if ((status4 & 0x00010000) != 0)
    				{
    						#ifdef	PCI_DEBUG
    		   			logMsg ("TX FIFO error : FIFO Empty\n",1,2,3,4,5,6);
    		   			#endif
    				}    	 				
    		   
    }
    if ((status3 & 0x00080000) != 0)
    {
    			#ifdef	PCI_DEBUG
    		   logMsg ("PCI TX COMMBUS : system error \n",1,2,3,4,5,6);
    		   /* reset tx controller */
    			 *PCITER |=0x80000000;
    			 volatile int i;
    			 for (i=0; i<100*4; i++) {};
     			 *PCITER &=0x7FFFFFFF;
    		  #endif
    }
    if ((status3 & 0x00040000) != 0)
    {
    			#ifdef	PCI_DEBUG
    		   logMsg ("PCI TX COMMBUS : retry error \n",1,2,3,4,5,6);
    		  #endif
    }
    if ((status3 & 0x00020000) != 0)
    {
    			#ifdef	PCI_DEBUG
    		   logMsg ("PCI TX COMMBUS : target abort\n",1,2,3,4,5,6);
    		  #endif
    }
    if ((status3 & 0x00010000) != 0)
    {
    			#ifdef	PCI_DEBUG
    		   logMsg ("PCI TX COMMBUS : initiator abort\n",1,2,3,4,5,6);
    		  #endif
    }
    
}
STATUS sysPciInit2
    (
    void
    )
    {
    volatile int i;
    /* initialize the communication TX PCI system */
    semBInit (&wrsyncSem, SEM_Q_FIFO, SEM_EMPTY);
    semBInit (&rdsyncSem, SEM_Q_FIFO, SEM_EMPTY);
    
    /* set the PCI command, MAX_Retries, and MAX_beats */
    *PCITTCR = 0x07050000;		/* write, retry 5, beats 8 */
    *PCIRTCR = 0x0C051000;		/*  read, retry 5, beats 8,full burst.. */
    
    /* reset FIFO */
    *PCITER |=0x40000000;
    *PCIRER |=0x40000000;
    for (i=0; i<100*4; i++) {};
    *PCITER &=0xBFFFFFFF;
    *PCIRER &=0xBFFFFFFF;
    
    /* alarm  set */
    *PCITFAR = 0x00000040;
    *PCIRFAR = 0x00000040;
    
    /*granularity set */
    *PCITFCR = 0x07200000;
		*PCIRFCR = 0x07200000;
		
		/* enable Master enable bit */
		*PCITER = 0x093F0000;
		*PCIRER = 0x293F0000;
    
#if defined(IS_LITE5200B) 
	/* LITE5200B used : /IRQ0 & /IRQ1 & /IRQ2 & /IRQ3*/
			pciIntrIrqA = (VOIDFUNCPTR)pciIntrIrq0;
			pciIntrIrqB = (VOIDFUNCPTR)pciIntrIrq1;
			pciIntrIrqC = (VOIDFUNCPTR)pciIntrIrq2;
			pciIntrIrqD = (VOIDFUNCPTR)pciIntrIrq3;
    	*ICTL_EEETR &= ~((UINT32)(ICTL_EEETR_MEE|ICTL_EEETR_ETYPE0_MASK|ICTL_EEETR_ETYPE1_MASK|ICTL_EEETR_ETYPE2_MASK|ICTL_EEETR_ETYPE3_MASK));
    	*ICTL_EEETR |= (ICTL_EEETR_ETYPE0_FALLING_EDGE|ICTL_EEETR_MEE|ICTL_EEETR_ETYPE1_FALLING_EDGE|ICTL_EEETR_ETYPE2_FALLING_EDGE|ICTL_EEETR_ETYPE3_FALLING_EDGE);
    	(void) intConnect ((VOIDFUNCPTR *)INUM_TO_IVEC (INUM_IRQ0),
		           (VOIDFUNCPTR)pciIntrIrqA, 0);
		  (void) intConnect ((VOIDFUNCPTR *)INUM_TO_IVEC (INUM_IRQ1),
		           (VOIDFUNCPTR)pciIntrIrqB, 0);
		  (void) intConnect ((VOIDFUNCPTR *)INUM_TO_IVEC (INUM_IRQ2),
		           (VOIDFUNCPTR)pciIntrIrqC, 0);
		  (void) intConnect ((VOIDFUNCPTR *)INUM_TO_IVEC (INUM_IRQ3),
		           (VOIDFUNCPTR)pciIntrIrqD, 0);
#endif
    intConnect (IV_PCI_CTL, pciCtlInt, 0);
    intEnable (INUM_PCI_CTL);
    intConnect (IV_PCI_RX, pciRxInt, 0);
    intEnable (INUM_PCI_RX);
    intConnect (IV_PCI_TX, pciTxInt, 0);
    intEnable (INUM_PCI_TX);
    TasksInitAPI((uint8*)MBAR_VALUE);
    intConnect (IV_SDMA_TASK0, (VOIDFUNCPTR)pciTxBestcommIntr, 0);
		intEnable(INUM_SDMA_TASK0);
    intConnect (IV_SDMA_TASK1, (VOIDFUNCPTR)pciRxBestcommIntr, 0);
		intEnable(INUM_SDMA_TASK1);
    *PCIICR  |= PCIICR_REE|PCIICR_IAE|PCIICR_TAE;
    *PCIGSCR |= PCIGSCR_BME|PCIGSCR_PEE|PCIGSCR_SEE;
    return OK;
    }

void *sysPciVectorMap(int pciIntLine)
{
    /* adjust interrupts value */
    if (pciIntLine >= NELEMENTS(vectorTbl))
	{
	return (NULL);
	}

    return vectorTbl[pciIntLine];		
}
void pciIntrIrq0()
{
	
	*ICTL_EEETR |= ICTL_EEETR_ECLR0_MASK;
	/* *PCI0_INTR_CLEAR = 0x10000000; */ 
	
}
void pciIntrIrq1()
{
	
	*ICTL_EEETR |= ICTL_EEETR_ECLR1_MASK;
	/* *PCI1_INTR_CLEAR = 0x10000000; */

}
void pciIntrIrq2()
{
	
	*ICTL_EEETR |= ICTL_EEETR_ECLR2_MASK;
	/* *PCI2_INTR_CLEAR = 0x10000000; */
	
}
void pciIntrIrq3()
{
	
	*ICTL_EEETR |= ICTL_EEETR_ECLR3_MASK;
	/* *PCI3_INTR_CLEAR = 0x10000000; */
	
}
void pciTxBestcommIntr()
{
	 if(TaskIntStatus(TaskTxPciId) == TaskTxPciId)
    {

      TaskIntClear(TaskTxPciId);
      intDisable(INUM_SDMA_TASK0);/*Disable ints*/
      semGive (&wrsyncSem);
    }
}

void pciRxBestcommIntr()
{
	 if(TaskIntStatus(TaskRxPciId) == TaskRxPciId)
    {

      TaskIntClear(TaskRxPciId);
      intDisable(INUM_SDMA_TASK1);/*Disable ints*/
      semGive (&rdsyncSem);
    }
}
STATUS PciBestcommRead(int *pSrcBuf, int *pDstBuf, int iLen)
{
		int semStatus;
		*PCIRSAR = (UINT32)pSrcBuf;
		TaskRxPciParam.Initiator = INITIATOR_SCPCI_RX;
		TaskRxPciParam.Size.NumBytes = iLen;
		TaskRxPciParam.IncrDst = SZ_UINT32;  /* Always for 32 Bits */
		TaskRxPciParam.SzDst = SZ_UINT32;
		TaskRxPciParam.StartAddrDst = (UINT32)pDstBuf;
		TaskRxPciId = TaskSetup(TASK_PCI_RX, &TaskRxPciParam);
		SDMA_CLEAR_IEVENT(SDMA_INT_PEND, TaskRxPciId);
		TaskStart(TaskRxPciId, TASK_AUTOSTART_DISABLE, TaskRxPciId, TASK_INTERRUPT_ENABLE);
		intEnable(INUM_SDMA_TASK1);
		*PCIRPSR = iLen;
		semStatus = semTake (&rdsyncSem, WAIT_FOREVER);
		SDMA_CLEAR_IEVENT(SDMA_INT_PEND, TaskRxPciId);
		TaskStop(TaskRxPciId);
		return (OK);
}

STATUS PciBestcommWrite(int *pSrcBuf, int *pDstBuf, int iLen)
{
		int semStatus;
		*PCITSAR = (UINT32)pDstBuf;
		TaskTxPciParam.Initiator = INITIATOR_SCPCI_TX;
		TaskTxPciParam.Size.NumBytes = iLen;
		TaskTxPciParam.IncrSrc = SZ_UINT32;  /* Always for 32 Bits */
		TaskTxPciParam.SzSrc = SZ_UINT32;
		TaskTxPciParam.StartAddrSrc = (UINT32)pSrcBuf;
		TaskTxPciId = TaskSetup(TASK_PCI_TX, &TaskTxPciParam);
		SDMA_CLEAR_IEVENT(SDMA_INT_PEND, TaskTxPciId);
		TaskStart(TaskTxPciId, TASK_AUTOSTART_DISABLE, TaskTxPciId, TASK_INTERRUPT_ENABLE);
		intEnable(INUM_SDMA_TASK0);
		*PCITPSR = iLen;
		semStatus = semTake (&wrsyncSem, WAIT_FOREVER);
		SDMA_CLEAR_IEVENT(SDMA_INT_PEND, TaskTxPciId);
		TaskStop(TaskTxPciId);
		return (OK);
}
#endif /* INCLUDE_PCI */