rominit.s

绝对可以转的vxworksbspfors3c44b0x。 8mhz晶振。

/* romInit.s - Samsung SBC ARM7 ROM initialization module */

/* Copyright 1984-2001 Wind River Systems, Inc. */

/*
modification history
--------------------
01f,18jan02,m_h  CLKCON initialization (74497), _sdata for vxWorks.res*
01e,30nov01,m_h  additional label with "_" on entry point functions
01d,15oct01,jb  Removing pre-pended underscores for new compilers (Diab/Gnu
                 elf)
01c,26apr01,m_h  fix thumb mode
01b,26apr01,m_h  convert tabs to spaces for readability
01a,12apr01,m_h  created from snds100 template.
*/

/*
DESCRIPTION
This module contains the entry code for VxWorks images that start
running from ROM, such as 'bootrom' and 'vxWorks_rom'.  The entry
point, romInit(), is the first code executed on power-up.  It performs
the minimal setup needed to call the generic C routine romStart() with
parameter BOOT_COLD.

romInit() masks interrupts in the processor and the interrupt
controller and sets the initial stack pointer (to STACK_ADRS which is
defined in configAll.h).  Other hardware and device initialisation is
performed later in the sysHwInit routine in sysLib.c.

The routine sysToMonitor() jumps to a location after the beginning of
romInit, (defined by ROM_WARM_ADRS) to perform a "warm boot".  This
entry point allows a parameter to be passed to romStart().

The routines in this module don't use the "C" frame pointer %r11@ ! or
establish a stack frame.

SEE ALSO:
.I "ARM Architecture Reference Manual,"
.I "Samsung KS32C50100 Microcontroller User's Manual,"
.I "Samsung KS32C5000(A)/50100 Microcontroller Application Notes."
*/

#define    _ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "arch/arm/arm.h"
#include "arch/arm/mmuArmLib.h"
#include "config.h"
#include "regs.h"    

    .data
    .globl   FUNC(copyright_wind_river)
    .long    FUNC(copyright_wind_river)

/* internals */

    .globl    FUNC(romInit)    /* start of system code */
    .globl    FUNC(sdata)      /* start of data */
    .globl    _sdata

/* externals */

    .globl    FUNC(romStart)    /* system initialization routine */

_sdata:
FUNC_LABEL(sdata)
    .asciz    "start of data"
    .balign    4

    .text
    .balign 4

/*******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*

* romInit
*     (
*     int startType    /@ only used by 2nd entry point @/
*     )

* INTERNAL
* sysToMonitor examines the ROM for the first instruction and the string
* "Copy" in the third word so if this changes, sysToMonitor must be updated.
*/

_ARM_FUNCTION(romInit)
_romInit:
    B       cold
    B       _romUndef
    B       _romSwi
    B       _romPrefetch
    B       _romDataAbort
    B       _romReserved         /* _romReserved */
    B       _romIRQ
    B       _romFIQ              /* _romFIQ     */
cold:
    MOV    r0, #BOOT_COLD    /* fall through to warm boot entry */	    
warm:
    B    start

    /* copyright notice appears at beginning of ROM (in TEXT segment) */

    .ascii   "Copyright 1984-2001 Wind River Systems, Inc."
    .balign 4

start:

    /*watch dog disable*/
    LDR    r2, L$_S3C44B0XWtcon
    MOV    r1, #0 
    STR    r1, [r2]
    
    /*all interrupt disable*/
    LDR    r2, L$_SBCARM7Intmsk
    MOV    r1, #0x07ffffff
    STR    r1, [r2]
    
    /*Set clock control registers*/
    /*LDR    r0, L$_SBCARM7Locktime
    MOV    r1, #0xfff
    STR    r1, [r0]*/
    LDR    r2, L$_SBCARM7Locktime
    LDR    r1, L$_LockTime
    STR    r1, [r2]
       
	/*temporary setting of PLL*/
    LDR    r2, L$_SBCARM7Pllcon
    LDR    r1, L$_PllCon
    STR    r1, [r2]

	/*All unit block CLK enable*/
    LDR    r2, L$_SBCARM7ClkCon
    LDR    r1, L$_ClkCon
    STR    r1, [r2]

      
#if 0    
    /* disable interrupts in CPU and switch to SVC32 mode */

    MRS    r1, cpsr
    BIC    r1, r1, #MASK_MODE
    ORR    r1, r1, #MODE_SVC32 | I_BIT | F_BIT
    MSR    cpsr, r1
#endif
    MOV    r14, r0    /* Save starttype in r13 so that r0 can be used for other purposes */
#if 0
    /*
     * CPU INTERRUPTS DISABLED
     *
     * disable individual interrupts in the interrupt controller
     */

    LDR    r2, L$_SBCARM7Intmsk        /* R2->interrupt controller */
    MVN    r1, #0                /* &FFFFFFFF */
    STR    r1, [r2]            /* disable all interrupt sources */
#endif    

    
    /*
     * If not BOOT_COLD, bypass memory configuration, memory region
     * switching etc.
     */
    CMP    r0, #BOOT_COLD
    BNE    HiPosn

    LDR    r0, L$_SBCARM7Syscfg
    LDR    r1, L$_SysCfgSdram
    STR    r1, [r0]             /* Cache,WB disable */

/* ROM and RAM Configuration(Multiple Load and Store).  Multiple load
 * LDMIA instruction cannot be used as there is no way to load the
 * address L$_SystemInitDataSDRAM into a register (LDR Rn,=sym is broken)
 */

    LDR    r1, L$_SystemInitDataSDRAM 
    LDR    r2, L$_SystemInitDataSDRAM + 0x04
    LDR    r3, L$_SystemInitDataSDRAM + 0x08
    LDR    r4, L$_SystemInitDataSDRAM + 0x0c
    LDR    r5, L$_SystemInitDataSDRAM + 0x10
    LDR    r6, L$_SystemInitDataSDRAM + 0x14
    LDR    r7, L$_SystemInitDataSDRAM + 0x18
    LDR    r8, L$_SystemInitDataSDRAM + 0x1c
    LDR    r9, L$_SystemInitDataSDRAM + 0x20
    LDR    r10,L$_SystemInitDataSDRAM + 0x24
    LDR    r11,L$_SystemInitDataSDRAM + 0x28
    LDR    r12,L$_SystemInitDataSDRAM + 0x2c
    LDR    r13,L$_SystemInitDataSDRAM + 0x30
    LDR    r0, L$_SBCARM7Extdbwth
    STMIA  r0, {r1-r13}




/*=============================================================
 * Copy to DRAM the section of ROM in which we are currently executing.
 * Soon, we will set the base pointer of DRAM to where the base pointer of
 * ROM used to be.  At that point the PC will suddenly be set in RAM and
 * must have legitimate code to execute.
 *=============================================================
 */
#if 0
    MOV    r0, #RESET_ROM_START         /* Get pointer to ROM data */
    LDR    r1, L$_RomCopySize           /* number of ROM bytes to copy into RAM */
    MOV    r2, #RESET_DRAM_START        /* Copy DRAM area base */

ROM2SDRAM_COPY_LOOP:
    LDR    r3, [r0], #4
    STR    r3, [r2], #4
    SUBS   r1, r1, #4         /* Down Count */
    BNE    ROM2SDRAM_COPY_LOOP
#endif

    LDR    PC, L$_HiPosn    

HiPosn:
    /*
     * Initialize the stack pointer to just before where the
     * uncompress code, copied from ROM to RAM, will run.
     */

    MOV    r0, r14        /* restore starttype to r0 from r13 */
    LDR    sp, L$_STACK_ADDR
    MOV    fp, #0            /* zero frame pointer */

    /* jump to C entry point in ROM: routine - entry point + ROM base */

#if    (CPU == ARMARCH4_T)
    LDR    r12, L$_rStrtInRom
    ORR    r12, r12, #1        /* force Thumb state */
    BX     r12
#else
    LDR    pc, L$_rStrtInRom
#endif    /* (CPU == ARMARCH4_T) */


    
_ARM_FUNCTION(romUndef)
_romUndef:
 sub sp, sp, #4
 stmfd sp!, {r0}
 ldr r0, L$_promUndef
 ldr r0, [r0]            
 str r0, [sp, #4]
 ldmfd sp!, {r0, pc}

_ARM_FUNCTION(romSwi)
_romSwi:
 sub sp, sp, #4
 stmfd sp!, {r0}
 ldr r0, L$_promSwi
 ldr r0, [r0]            
 str r0, [sp, #4]
 ldmfd sp!, {r0, pc}

_ARM_FUNCTION(romPrefetch)
_romPrefetch:
 sub sp, sp, #4
 stmfd sp!, {r0}
 ldr r0, L$_promPrefetch
 ldr r0, [r0]            
 str r0, [sp, #4]
 ldmfd sp!, {r0, pc}  

_ARM_FUNCTION(romDataAbort)
_romDataAbort:
 sub sp, sp, #4
 stmfd sp!, {r0}
 ldr r0, L$_promDataAbort
 ldr r0, [r0]            
 str r0, [sp, #4]
 ldmfd sp!, {r0, pc}
 
_ARM_FUNCTION(romReserved)
_romReserved:
 sub sp, sp, #4
 stmfd sp!, {r0}
 ldr r0, L$_promReserved
 ldr r0, [r0]            
 str r0, [sp, #4]
 ldmfd sp!, {r0, pc} 

_ARM_FUNCTION(romIRQ)
_romIRQ:
 sub sp, sp, #4
 stmfd sp!, {r0}
 ldr r0, L$_promIRQ
 ldr r0, [r0]            
 str r0, [sp, #4]
 ldmfd sp!, {r0, pc} 

_ARM_FUNCTION(romFIQ)
_romFIQ:
 sub sp, sp, #4
 stmfd sp!, {r0}
 ldr r0, L$_promFIQ
 ldr r0, [r0]            
 str r0, [sp, #4]
 ldmfd sp!, {r0, pc} 
   
/******************************************************************************/

/*
 * PC-relative-addressable pointers - LDR Rn,=sym is broken
 * note "_" after "$" to stop preprocessor preforming substitution
 */

    .balign    4

#ifdef SIM
L$_HiPosn:
    .long    RAM_HIGH_ADRS + HiPosn - FUNC(romInit)
#else
L$_HiPosn:
    .long    ROM_TEXT_ADRS + HiPosn - FUNC(romInit)
#endif

#ifdef SIM
L$_rStrtInRom:
    .long    RAM_HIGH_ADRS + FUNC(romStart) - FUNC(romInit)
#else
L$_rStrtInRom:    
    .long    ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)
#endif

L$_STACK_ADDR:
    .long    STACK_ADRS

L$_SBCARM7Intmsk:
    .long    S3C44B0X_INTMSK

L$_SBCARM7Pllcon:
    .long    S3C44B0X_PLLCON    

L$_SBCARM7Locktime:
    .long    S3C44B0X_LOCKTIME    


L$_S3C44B0XWtcon:
    .long    S3C44B0X_WTCON

/*L$_IopModReg:
    .long    SNGKS32C_IOPMOD*/

/*L$_IopConReg:
    .long    SNGKS32C_IOPCON*/

/*L$_IopDat:
    .long    SNGKS32C_IOPDATA*/

L$_SBCARM7Romcon0:
    .long    S3C44B0X_BANKCON0

L$_SBCARM7Extdbwth:
    .long    S3C44B0X_BWSCON

L$_SBCARM7Syscfg:
    .long    S3C44B0X_SYSCFG

/*L$_SysCfg:
    .long    SYSCONFIG_VAL*/

L$_SysCfgSdram:
    .long    SYSCONFIG_VAL_SDRAM

L$_SBCARM7ClkCon:
    .long    S3C44B0X_CLKCON

L$_ClkCon:
    .long    rCLKCON

L$_PllCon:
    .long    rPLLCON
    
L$_LockTime:
    .long    rLOCKTIME
    
/*L$_SBCARM7ExtACon:
    .long    SNGKS32C_EXTACON0
    .long    SNGKS32C_EXTACON1*/

/*L$_ExtACon:
    .long    rEXTACON0
    .long    rEXTACON1*/
#if 0
L$_SystemInitData:
    .long    rEXTDBWTH    /* DRAM1(Half), ROM5(Byte), ROM1(Half), else 32bit */
    .long    rROMCON0     /* 0x0000000 ~ 0x40000, ROM0,256K,2cycle */
    .long    rROMCON1 
    .long    rROMCON2
    .long    rROMCON3
    .long    rROMCON4
    .long    rROMCON5
    .long    rDRAMCON0    /* 0x1000000 ~ 0x13FFFFF, DRAM0 4M, */
    .long    rDRAMCON1
    .long    rDRAMCON2
    .long    rDRAMCON3
    .long    rREFEXTCON    /* External I/O, Refresh */

L$_SystemInitData_S:
    .long    rEXTDBWTH    /* DRAM1(Half), ROM5(Byte), ROM1(Half), else 32bit */
    .long    rROMCON0_S    /* 0x1000000 ~ 0x1040000, ROM0,256K,2cycle */
    .long    rROMCON1
    .long    rROMCON2
    .long    rROMCON3
    .long    rROMCON4
    .long    rROMCON5
    .long    rDRAMCON0_S     /* 0x0000000 ~ 0x03FFFFF, DRAM0 */
    .long    rDRAMCON1
    .long    rDRAMCON2
    .long    rDRAMCON3
    .long    rREFEXTCON    /* External I/O, Refresh */
#endif
/*======================================================
 * SDRAM System Initialize Data (KS32C50100 only)
 *======================================================
 */
L$_SystemInitDataSDRAM:
    .long    rEXTDBWTH    
    .long    rROMCON0    
    .long    rROMCON1
    .long    rROMCON2
    .long    rROMCON3
    .long    rROMCON4
    .long    rROMCON5
    .long    rSDRAMCON0
    .long    rSDRAMCON1
    .long    rSREFEXTCON
    .long    rBANKSIZE
    .long    rMRSRB6
    .long    rMRSRB7
        
#if 0
L$_SystemInitDataSDRAM_S:
    .long    rEXTDBWTH    /* DRAM1(Half), ROM5(Byte), ROM1(Half), else 32bit */
    .long    rROMCON0_S    /* 0x1000000 ~ 0x1040000, ROM0,256K,2cycle */
    .long    rROMCON1
    .long    rROMCON2
    .long    rROMCON3
    .long    rROMCON4
    .long    rROMCON5
    .long    rSDRAMCON0_S    /* 0x0000000 ~ 0x03FFFFF, DRAM0 4M, */
    .long    rSDRAMCON1
    .long    rSDRAMCON2
    .long    rSDRAMCON3
    .long    rSREFEXTCON    /* External I/O, Refresh */
#endif
/*L$_pSystemInitData:
    .long    L$_SystemInitData

L$_pSystemInitData_S:
    .long    L$_SystemInitData_S*/

L$_pSystemInitDataSDRAM:
    .long    L$_SystemInitDataSDRAM

/*L$_pSystemInitDataSDRAM_S:
    .long    L$_SystemInitDataSDRAM_S*/

L$_promUndef:
    .long     S3C_EXC_BASE
L$_promSwi:
    .long     S3C_EXC_BASE + 4
L$_promPrefetch:
    .long     S3C_EXC_BASE + 8
L$_promDataAbort:
    .long     S3C_EXC_BASE + 12
L$_promReserved:
    .long     S3C_EXC_BASE + 16
L$_promIRQ:
    .long     S3C_EXC_BASE + 20
L$_promFIQ:
    .long     S3C_EXC_BASE + 24
    
L$_RomCopySize:
    .long    L$_RomCopySize - FUNC(romInit)