cnt10.tan.rpt

led 跑马灯

; tco                                                                ;
+-------+--------------+------------+--------+----------+------------+
; Slack ; Required tco ; Actual tco ; From   ; To       ; From Clock ;
+-------+--------------+------------+--------+----------+------------+
; N/A   ; None         ; 7.906 ns   ; tmp[0] ; led7s[3] ; clk        ;
; N/A   ; None         ; 7.900 ns   ; tmp[0] ; led7s[1] ; clk        ;
; N/A   ; None         ; 7.899 ns   ; tmp[0] ; led7s[6] ; clk        ;
; N/A   ; None         ; 7.898 ns   ; tmp[0] ; led7s[2] ; clk        ;
; N/A   ; None         ; 7.889 ns   ; tmp[0] ; led7s[5] ; clk        ;
; N/A   ; None         ; 7.886 ns   ; tmp[0] ; led7s[0] ; clk        ;
; N/A   ; None         ; 7.770 ns   ; tmp[2] ; led7s[2] ; clk        ;
; N/A   ; None         ; 7.766 ns   ; tmp[2] ; led7s[5] ; clk        ;
; N/A   ; None         ; 7.766 ns   ; tmp[2] ; led7s[0] ; clk        ;
; N/A   ; None         ; 7.762 ns   ; tmp[2] ; led7s[6] ; clk        ;
; N/A   ; None         ; 7.754 ns   ; tmp[2] ; led7s[3] ; clk        ;
; N/A   ; None         ; 7.753 ns   ; tmp[2] ; led7s[1] ; clk        ;
; N/A   ; None         ; 7.489 ns   ; tmp[1] ; led7s[2] ; clk        ;
; N/A   ; None         ; 7.486 ns   ; tmp[1] ; led7s[0] ; clk        ;
; N/A   ; None         ; 7.485 ns   ; tmp[1] ; led7s[5] ; clk        ;
; N/A   ; None         ; 7.483 ns   ; tmp[1] ; led7s[3] ; clk        ;
; N/A   ; None         ; 7.479 ns   ; tmp[1] ; led7s[6] ; clk        ;
; N/A   ; None         ; 7.475 ns   ; tmp[1] ; led7s[1] ; clk        ;
; N/A   ; None         ; 7.454 ns   ; tmp[0] ; led7s[4] ; clk        ;
; N/A   ; None         ; 7.321 ns   ; tmp[2] ; led7s[4] ; clk        ;
; N/A   ; None         ; 7.039 ns   ; tmp[1] ; led7s[4] ; clk        ;
+-------+--------------+------------+--------+----------+------------+


+--------------------------------------------------------------------+
; th                                                                 ;
+---------------+-------------+-----------+------+--------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To     ; To Clock ;
+---------------+-------------+-----------+------+--------+----------+
; N/A           ; None        ; -4.650 ns ; en   ; tmp[0] ; clk      ;
; N/A           ; None        ; -4.650 ns ; en   ; tmp[2] ; clk      ;
; N/A           ; None        ; -4.650 ns ; en   ; tmp[1] ; clk      ;
+---------------+-------------+-----------+------+--------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Sun Apr 27 12:25:59 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cnt10 -c cnt10 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "tmp[1]" and destination register "tmp[2]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.293 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y10_N3; Fanout = 9; REG Node = 'tmp[1]'
            Info: 2: + IC(0.686 ns) + CELL(0.607 ns) = 1.293 ns; Loc. = LC_X26_Y10_N0; Fanout = 8; REG Node = 'tmp[2]'
            Info: Total cell delay = 0.607 ns ( 46.95 % )
            Info: Total interconnect delay = 0.686 ns ( 53.05 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.782 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 3; CLK Node = 'clk'
                Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X26_Y10_N0; Fanout = 8; REG Node = 'tmp[2]'
                Info: Total cell delay = 2.180 ns ( 78.36 % )
                Info: Total interconnect delay = 0.602 ns ( 21.64 % )
            Info: - Longest clock path from clock "clk" to source register is 2.782 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 3; CLK Node = 'clk'
                Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X26_Y10_N3; Fanout = 9; REG Node = 'tmp[1]'
                Info: Total cell delay = 2.180 ns ( 78.36 % )
                Info: Total interconnect delay = 0.602 ns ( 21.64 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "tmp[0]" (data pin = "en", clock pin = "clk") is 4.702 ns
    Info: + Longest pin to register delay is 7.447 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_107; Fanout = 3; PIN Node = 'en'
        Info: 2: + IC(5.111 ns) + CELL(0.867 ns) = 7.447 ns; Loc. = LC_X26_Y10_N6; Fanout = 10; REG Node = 'tmp[0]'
        Info: Total cell delay = 2.336 ns ( 31.37 % )
        Info: Total interconnect delay = 5.111 ns ( 68.63 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.782 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 3; CLK Node = 'clk'
        Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X26_Y10_N6; Fanout = 10; REG Node = 'tmp[0]'
        Info: Total cell delay = 2.180 ns ( 78.36 % )
        Info: Total interconnect delay = 0.602 ns ( 21.64 % )
Info: tco from clock "clk" to destination pin "led7s[3]" through register "tmp[0]" is 7.906 ns
    Info: + Longest clock path from clock "clk" to source register is 2.782 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 3; CLK Node = 'clk'
        Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X26_Y10_N6; Fanout = 10; REG Node = 'tmp[0]'
        Info: Total cell delay = 2.180 ns ( 78.36 % )
        Info: Total interconnect delay = 0.602 ns ( 21.64 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y10_N6; Fanout = 10; REG Node = 'tmp[0]'
        Info: 2: + IC(0.654 ns) + CELL(0.590 ns) = 1.244 ns; Loc. = LC_X26_Y10_N1; Fanout = 1; COMB Node = 'Mux3~25'
        Info: 3: + IC(1.532 ns) + CELL(2.124 ns) = 4.900 ns; Loc. = PIN_98; Fanout = 0; PIN Node = 'led7s[3]'
        Info: Total cell delay = 2.714 ns ( 55.39 % )
        Info: Total interconnect delay = 2.186 ns ( 44.61 % )
Info: th for register "tmp[0]" (data pin = "en", clock pin = "clk") is -4.650 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.782 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 3; CLK Node = 'clk'
        Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X26_Y10_N6; Fanout = 10; REG Node = 'tmp[0]'
        Info: Total cell delay = 2.180 ns ( 78.36 % )
        Info: Total interconnect delay = 0.602 ns ( 21.64 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 7.447 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_107; Fanout = 3; PIN Node = 'en'
        Info: 2: + IC(5.111 ns) + CELL(0.867 ns) = 7.447 ns; Loc. = LC_X26_Y10_N6; Fanout = 10; REG Node = 'tmp[0]'
        Info: Total cell delay = 2.336 ns ( 31.37 % )
        Info: Total interconnect delay = 5.111 ns ( 68.63 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Apr 27 12:25:59 2008
    Info: Elapsed time: 00:00:01