cnt10.sim.rpt

led 跑马灯

; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      62.09 % ;
; Total nodes checked                                 ; 551          ;
; Total output ports checked                          ; 554          ;
; Total output ports with complete 1/0-value coverage ; 344          ;
; Total output ports with no 1/0-value coverage       ; 210          ;
; Total output ports with no 1-value coverage         ; 210          ;
; Total output ports with no 0-value coverage         ; 210          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                           ;
+-----------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+
; Node Name                                                             ; Output Port Name                                                           ; Output Port Type ;
+-----------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+
; |cnt10|tmp~0                                                          ; |cnt10|tmp~0                                                               ; out              ;
; |cnt10|tmp~1                                                          ; |cnt10|tmp~1                                                               ; out              ;
; |cnt10|tmp~2                                                          ; |cnt10|tmp~2                                                               ; out              ;
; |cnt10|tmp~3                                                          ; |cnt10|tmp~3                                                               ; out              ;
; |cnt10|tmp[0]                                                         ; |cnt10|tmp[0]                                                              ; out              ;
; |cnt10|tmp[1]                                                         ; |cnt10|tmp[1]                                                              ; out              ;
; |cnt10|tmp[2]                                                         ; |cnt10|tmp[2]                                                              ; out              ;
; |cnt10|clrn                                                           ; |cnt10|clrn                                                                ; out              ;
; |cnt10|clk                                                            ; |cnt10|clk                                                                 ; out              ;
; |cnt10|en                                                             ; |cnt10|en                                                                  ; out              ;
; |cnt10|led7s[0]                                                       ; |cnt10|led7s[0]                                                            ; pin_out          ;
; |cnt10|led7s[1]                                                       ; |cnt10|led7s[1]                                                            ; pin_out          ;
; |cnt10|led7s[2]                                                       ; |cnt10|led7s[2]                                                            ; pin_out          ;
; |cnt10|led7s[3]                                                       ; |cnt10|led7s[3]                                                            ; pin_out          ;
; |cnt10|led7s[4]                                                       ; |cnt10|led7s[4]                                                            ; pin_out          ;
; |cnt10|led7s[5]                                                       ; |cnt10|led7s[5]                                                            ; pin_out          ;
; |cnt10|led7s[6]                                                       ; |cnt10|led7s[6]                                                            ; pin_out          ;
; |cnt10|LessThan0~16                                                   ; |cnt10|LessThan0~16                                                        ; out0             ;
; |cnt10|LessThan0~17                                                   ; |cnt10|LessThan0~17                                                        ; out0             ;
; |cnt10|LessThan0~18                                                   ; |cnt10|LessThan0~18                                                        ; out0             ;
; |cnt10|LessThan0~19                                                   ; |cnt10|LessThan0~19                                                        ; out0             ;
; |cnt10|LessThan0~20                                                   ; |cnt10|LessThan0~20                                                        ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~1                        ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~1                             ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~2                        ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~2                             ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~3                        ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~3                             ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|result_node[0]~1           ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|result_node[0]~1                ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|result_node[0]             ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|result_node[0]                  ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~4                        ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~4                             ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~6                        ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~6                             ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~7                        ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~7                             ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result112w~1             ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result112w~1                  ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result112w               ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result112w                    ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~8                        ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~8                             ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~10                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~10                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~11                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~11                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result129w~1             ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result129w~1                  ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result129w               ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result129w                    ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~13                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~13                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~14                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~14                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result145w~0             ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result145w~0                  ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~15                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~15                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result145w               ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result145w                    ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~16                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~16                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~17                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~17                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result60w~0              ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result60w~0                   ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~18                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~18                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~19                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~19                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result60w                ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result60w                     ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~21                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~21                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~22                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~22                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~23                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~23                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~25                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~25                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~26                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~26                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~27                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~27                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~29                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~29                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~30                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~30                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~31                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~31                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~32                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~32                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~34                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~34                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~35                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~35                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result74w~1              ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result74w~1                   ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result74w                ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result74w                     ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~36                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~36                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~38                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~38                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~39                       ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|_~39                            ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result95w~1              ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result95w~1                   ; out0             ;
; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result95w                ; |cnt10|lpm_mux:Mux6|mux_3ec:auto_generated|w_result95w                     ; out0             ;
; |cnt10|lpm_mux:Mux5|mux_3ec:auto_generated|_~1                        ; |cnt10|lpm_mux:Mux5|mux_3ec:auto_generated|_~1                             ; out0             ;
; |cnt10|lpm_mux:Mux5|mux_3ec:auto_generated|_~2                        ; |cnt10|lpm_mux:Mux5|mux_3ec:auto_generated|_~2                             ; out0             ;
; |cnt10|lpm_mux:Mux5|mux_3ec:auto_generated|_~3                        ; |cnt10|lpm_mux:Mux5|mux_3ec:auto_generated|_~3                             ; out0             ;
; |cnt10|lpm_mux:Mux5|mux_3ec:auto_generated|result_node[0]~1           ; |cnt10|lpm_mux:Mux5|mux_3ec:auto_generated|result_node[0]~1                ; out0             ;
; |cnt10|lpm_mux:Mux5|mux_3ec:auto_generated|result_node[0]             ; |cnt10|lpm_mux:Mux5|mux_3ec:auto_generated|result_node[0]                  ; out0             ;
; |cnt10|lpm_mux:Mux5|mux_3ec:auto_generated|_~4                        ; |cnt10|lpm_mux:Mux5|mux_3ec:auto_generated|_~4                             ; out0             ;