usbisp1582.h

vxworks 6.x 的全部头文件

/* usbIsp1582.h - Definitions for Philips ISP 1582 USB target controller */

/* Copyright 2004 Wind River Systems, Inc. */

/*
Modification history
--------------------
01b,15jun04,hch  Merge after ISP1582 driver testing done on MIPS, SH.
01b,19jul04,ami Coding Convention Changes
01a,19apr04,ami First
*/

/*
DESCRIPTION

Defines constants related to the Philips ISP 1582 USB device (target) IC.
*/

#ifndef __INCusbIsp1582h
#define __INCusbIsp1582h

#ifdef	__cplusplus
extern "C" {
#endif


/* defines */

/* ISP 1582 Endpoint Index */

#define ISP1582_ENDPT_0_RX               0x0  /* Control Out Endpoint  */
#define ISP1582_ENDPT_1_RX               0x2  /* Out Endpoint 1 */
#define ISP1582_ENDPT_2_RX               0x4  /* Out Endpoint 2 */
#define ISP1582_ENDPT_3_RX               0x6  /* Out Endpoint 3 */
#define ISP1582_ENDPT_4_RX               0x8  /* Out Endpoint 4 */
#define ISP1582_ENDPT_5_RX               0xA  /* Out Endpoint 5 */
#define ISP1582_ENDPT_6_RX               0xC  /* Out Endpoint 6 */
#define ISP1582_ENDPT_7_RX               0xE  /* Out Endpoint 7 */

#define ISP1582_ENDPT_0_TX               0x1  /* Control In Endpoint */
#define ISP1582_ENDPT_1_TX               0x3  /* In Endpoint 1 */
#define ISP1582_ENDPT_2_TX               0x5  /* In Endpoint 2 */
#define ISP1582_ENDPT_3_TX               0x7  /* In Endpoint 3 */
#define ISP1582_ENDPT_4_TX               0x9  /* In Endpoint 4 */
#define ISP1582_ENDPT_5_TX               0xB  /* In Endpoint 5 */
#define ISP1582_ENDPT_6_TX               0xD  /* In Endpoint 6 */
#define ISP1582_ENDPT_7_TX               0xF  /* In Endpoint 7 */

/* ISP 1582 I/O registers */

/* Initialization Registers */
#define ISP1582_ADDRESS_REG              0x00     /* Address Register */
#define ISP1582_MODE_REG                 0x0C     /* Mode Register */
#define ISP1582_INT_CONFIG_REG           0x10     /* Interrupt Config. Reg. */
#define ISP_1582_OTG_REG                 0x12     /* OTG Register */
#define ISP_1582_INT_ENABLE_REG          0x14     /* Interrupt Enable Reg. */

/* Dataflow Registers */
#define ISP1582_ENDPT_INDEX_REG          0x2C   /* Endpoint Index Register */
#define ISP1582_CNTL_FUNC_REG            0x28   /* Control Function Register */
#define ISP1582_DATA_PORT_REG            0x20   /* Data Port Register */
#define ISP1582_BUF_LEN_REG              0x1C   /* Buffer Length Register */
#define ISP1582_BUF_STATUS_REG           0x1E   /* Buffer Status Register */
#define ISP1582_ENDPT_MAXPSIZE_REG       0x04   /* Max. Packet Size Register */
#define ISP1582_ENDPT_TYPE_REG           0x08   /* Endpoint Type Regsiter */

/* DMA Registers */
#define ISP1582_DMA_COMMAND_REG          0x30   /* DMA Command Register */
#define ISP1582_DMA_TRANS_CNT_REG        0x34   /* DMA Transfer Counter Reg. */
#define ISP1582_DMA_CONFIG_REG           0x38   /* DMA Config. Register */
#define ISP1582_DMA_HARDWARE_REG         0x3C   /* DMA Hardware Register */
#define ISP1582_DMA_INT_RESN_REG         0x50   /* DMA Interrupt Reason Reg */
#define ISP1582_DMA_INT_ENBL_REG         0x54   /* DMA Interrupt Enable Reg. */
#define ISP1582_DMA_ENDPT_REG            0x58   /* DMA Endpoint Regsiter */
#define ISP1582_DMA_BURST_COUNT_REG      0x64   /* DMA Burst Count Regsiter */

/* General Register */
#define ISP1582_INT_REG                  0x18   /* Interrupt Register */
#define ISP1582_CHIP_ID_REG              0x70   /* Chip ID */
#define ISP1582_FRM_NUM_REG              0x74   /* Frame Number Register */
#define ISP1582_SCRATCH_REG              0x78   /* Scratch Regsiter */
#define ISP1582_UNLOCK_DEV_REG           0x7C   /* Device Unlock Register */
#define ISP1582_TEST_MODE_REG            0x84   /* Test Mode Regsiter */

/* ISP 1582 endpoints */

#define ISP1582_NUM_ENDPOINTS		     16	   /* number of endpoints */

/* Maximum FIFO Size */
#define ISP1582_FIFO_SIZE                8192  /* 8 KBytes */

/* address register (read/write 1 byte) */

#define ISP1582_ADRS_REG_ADRS_MASK       0x7f    /* address bits */
#define ISP1582_ADRS_REG_ENABLE          0x80    /* enable bit */

/* mode register (read/write 2 bytes) */

#define ISP1582_MODE_REG_MASK            0x03FF  /* Mode Regsiter Mask */
#define ISP1582_MODE_REG_SOFTCT          0x0001  /* Soft Connect */
#define ISP1582_MODE_REG_POWRON          0x0002  /* Power On */
#define ISP1582_MODE_REG_WKUPCS          0x0004  /* Wake Up on Select */
#define ISP1582_MODE_REG_GLINTENA        0x0008  /* Global Interrupt Enable */
#define ISP1582_MODE_REG_SFRESET         0x0010  /* Soft Reset */
#define ISP1582_MODE_REG_GOSUSP          0x0020  /* Suspend Mode */
#define ISP1582_MODE_REG_SNDRSU          0x0040  /* Resume Signal */
#define ISP1582_MODE_REG_CLKAON          0x0080  /* Clock Always On */
#define ISP1582_MODE_REG_VBUSSTAT        0x0100  /* V-Bus Status */
#define ISP1582_MODE_REG_DMACLKON        0x0200  /* DMA Clock Always On */

/* interupt configuration register (read/write 1 byte) */

/* Control Debugging Modes */
#define ISP1582_INT_CONF_REG_CDBGMOD_MASK        0xC0 /* Control Mode Mask */
#define ISP1582_INT_CONF_REG_CDBGMOD_ACK_NAK     0x00 /* Interrupts on all */
                                                      /*ACKS & NAKS on Control */
                                                      /* Endpoint */

#define ISP1582_INT_CONF_REG_CDBGMOD_ACK_ONLY    0x01 /* Interrupts on only */
                                                      /* ACKS on Control */
                                                      /* Endpoint */
#define ISP1582_INT_CONF_REG_CDBGMOD_ACK_FST_NAK 0x02 /*Interrupts on all ACKS */
                                                      /* and first NAK on */
                                                      /* control endpoint */
#define ISP1582_INT_CONF_REG_CDBGMOD_SHIFT(b)    ((b)<<6) /* Shift Value */

/* Data Debug Mode IN */
#define ISP1582_INT_CONF_REG_DDBGMODIN_MASK        0x30 /* Data Debug Mode IN */
                                                        /* Mask Value*/
#define ISP1582_INT_CONF_REG_DDBGMODIN_ACK_NAK     0x00 /* Interrupts on */
                                                        /* ACKs and NAKs on */
                                                        /* IN Endpoint */
#define ISP1582_INT_CONF_REG_DDBGMODIN_ACK_ONLY    0x01 /* Interrupts on only */
                                                        /* ACKS on IN Endpoint*/

#define ISP1582_INT_CONF_REG_DDBGMODIN_ACK_FST_NAK 0x02 /* Interrupts on all */
                                                        /* ACKS and first NAK */
                                                        /* on IN endpoint */
#define ISP1582_INT_CONF_REG_DDBGMODIN_SHIFT(b)    ((b)<<4) /* Shift Value */

/* Data Debug Mode Out */
#define ISP1582_INT_CONF_REG_DDBGMODOUT_MASK       0x0C /* Data Debug Mode OUT*/
                                                        /* Mask Value */
#define ISP1582_INT_CONF_REG_DDBGMODOUT_ACK_NAK_NYET  0x00 /* Interrupts on */
                                                           /* ACKs, NYETs and */
                                                           /* NAKs on OUT */
                                                           /* Endpoint */
#define ISP1582_INT_CONF_REG_DDBGMODOUT_ACK_NYET  0x01  /* Interrupts on only */
                                                        /* ACKS & NYETs on */
                                                        /* OUT Endpoint */

#define ISP1582_INT_CONF_REG_DDBGMODOUT_ACK__NYET_FST_NAK  0x02 /* Interrupts */
                                                                /* on ACKS, */
                                                                /* NYETs &  */
                                                                /* first NAK */

#define ISP1582_INT_CONF_REG_DDBGMODOUT_SHIFT(b)  ((b)<<2) /* Shift Value */

/* Interrupt Level Bit */
#define ISP1582_INT_CONF_REG_INTLVL_PULSED      0x02   /* Pulsed Mode */

/* Interrupt Polarity Bit */
#define ISP1582_INT_CONF_REG_INTPOL_HIGH       0x01    /* Polarity */


/* Interrupt Enable Register (read/write 4 bytes) */

#define ISP1582_INT_ENABLE_REG_MASK       0x03FFFFFF /* Mask Value */
#define ISP1582_INT_ENABLE_REG_IEBRST     0x0001  /* Bus Reset */
#define ISP1582_INT_ENABLE_REG_IESOF      0x0002  /* Start of Frame */
#define ISP1582_INT_ENABLE_REG_IEPSOF     0x0004  /* Pseudo Start of Frame */
#define ISP1582_INT_ENABLE_REG_IESUSP     0x0008  /* Suspend */
#define ISP1582_INT_ENABLE_REG_IERESM     0x0010  /* Resume */
#define ISP1582_INT_ENABLE_REG_IEHS_STA   0x0020  /* High Speed Detection */
#define ISP1582_INT_ENABLE_REG_IEDMA      0x0040  /* DMA */
#define ISP1582_INT_ENABLE_REG_IEVBUS     0x0080  /* V-Bus Detection */
#define ISP1582_INT_ENABLE_REG_IEP0SETUP  0x0100  /* Setup Buffer on Endpt 0 */