usbnet2280.h

vxworks 6.x 的全部头文件

#define NET2280_XIRQENB0_EP(x)		(1 << x)
#define NET2280_XIRQENB0_MASK           0x000000FF   

#define NET2280_XIRQENB1_REG_MASK	0x8E1B3FDF  /* Reg. Mask */
#define NET2280_XIRQENB1_INTEN		0x80000000  /* XIRQENB1: PCI INT Enable*/
#define NET2280_XIRQENB1_PSCINTEN	0x08000000  /* XIRQENB1: PWR State */
                                                    /* Change Interrupt Enable */ 	
#define NET2280_XIRQENB1_PCIARTTIMEOUT  0x04000000  /* XIRQENB1: PCI Arbiter */
						    /* Timeout Interrupt Enable */
#define NET2280_XIRQENB1_PCIPARITYERR	0x02000000  /* PCI Parity Error */
#define NET2280_XIRQENB1_PCIRTYABORT	0x00020000  /* PCI Retry Abort */	
#define NET2280_XIRQENB1_PCIMASCYCLEDN	0x00010000  /* PCI Master Cycle Done */	
#define NET2280_XIRQENB1_GPIO		0x00002000  /* General I/O */	
#define NET2280_XIRQENB1_DMA(x)		(0x00000100 << x) /* DMA Int Enable */
#define NET2280_XIRQENB1_EEPD		0x00000100	/* EEPROM done */
#define NET2280_XIRQENB1_VBUS		0x00000080	/* VBUS change */
#define NET2280_XIRQENB1_CS		0x00000040	/* control status */
#define NET2280_XIRQENB1_RPRESET	0x00000010	/* root port reset */
#define NET2280_XIRQENB1_SUSP		0x00000008	/* suspend request */
#define NET2280_XIRQENB1_SUSREQCHG	0x00000004	/* susp. req. change */
#define NET2280_XIRQENB1_RESM		0x00000002	/* resume */
#define NET2280_XIRQENB1_SOF		0x00000001	/* start-of-frame */

/* Interrupt status registers - status bits are cleared by writing a 1 */

#define NET2280_IRQENB0_SETUP		0x00000080
#define NET2280_IRQENB0_EP(x)		(1 << x)
#define NET2280_IRQENB0_EPMASK          0x0000007F

#define NET2280_IRQENB1_REG_MASK	0x8E1B3FDF  /* Reg. Mask */
#define NET2280_IRQENB1_INTEN		0x80000000  /* IRQENB1: PCI INT */
#define NET2280_IRQENB1_PSCINTEN	0x08000000  /* IRQENB1: PWR State */
                                                    /* Change Interrupt */
#define NET2280_IRQENB1_PCIARTTIMEOUT  0x04000000  /* XIRQENB1: PCI Arbiter */
						    /* Timeout Interrupt */
#define NET2280_IRQENB1_PCIPARITYERR	0x02000000  /* PCI Parity Error */
#define NET2280_IRQENB1_PCIRTYABORT	0x00020000  /* PCI Retry Abort */
#define NET2280_IRQENB1_PCIMASCYCLEDN	0x00010000  /* PCI Master Cycle Done */
#define NET2280_IRQENB1_GPIO		0x00002000  /* General I/O */
#define NET2280_IRQENB1_DMA(x)		(0x00000100 << x) /* DMA Int */
#define NET2280_IRQENB1_EEPD		0x00000100	/* EEPROM done */
#define NET2280_IRQENB1_VBUS		0x00000080	/* VBUS change */
#define NET2280_IRQENB1_CS		0x00000040	/* control status */
#define NET2280_IRQENB1_RPRESET	        0x00000010	/* root port reset */
#define NET2280_IRQENB1_SUSP		0x00000008	/* suspend request */
#define NET2280_IRQENB1_SUSREQCHG	0x00000004	/* susp. req. change */
#define NET2280_IRQENB1_RESM		0x00000002	/* resume */
#define NET2280_IRQENB1_SOF		0x00000001	/* start-of-frame */
#define NET2280_IRQENB1_DMA_SHIFT       9               /* DMA shift value */

/* DMA registers */

#define NET2280_DMACTL_SG_INT_EN	0x02000000	/* scatter/gather int */
#define NET2280_DMACTL_SGE		0x00010000	/* scatter/gather en */
#define NET2280_DMACTL_ASE		0x00000010	/* auto start enable */
#define NET2280_DMACTL_PREENB		0x00000008	/* dma preempt enable */
#define NET2280_DMACTL_FIFOVAL		0x00000004	/* dma fifo validate */
#define NET2280_DMACTL_EN		0x00000002	/* dma enable */
#define NET2280_DMACTL_ADDRHOLD		0x00000001	/* dma address hold */

#define NET2280_DMASTAT_SG_INT		0x02000000	/* scatter/gather */
#define NET2280_DMASTAT_TD_INT		0x01000000	/* transact. done */
#define NET2280_DMASTAT_ABORT		0x00000002	/* abort DMA trans. */
#define NET2280_DMASTAT_START		0x00000001	/* start DMA trans. */

#define NET2280_DMACOUNT_VB		0x80000000	/* DMA valid bit */
#define NET2280_DMACOUNT_DIR		0x40000000	/* DMA direction */
#define NET2280_DMACOUNT_DIE		0x20000000	/* done int. enable */
#define	NET2280_DMACOUNT_BC		0x00FFFFFF	/* Byte count */

/* Test Mode Register */

#define NET2280_XCVRDIAG_TEST_MASK      0x07000000    /* XCVRDIAG: Mask bits */
#define NET2280_XCVRDIAG_TEST_SHIFT_VAL 24
#define NET2280_XCVRDIAG_TEST_MODE_SET(x) \
                                        ((x) << NET2280_XCVRDIAG_TEST_SHIFT_VAL)

/* Endpoint registers */
#define NET2280_EP_STAT_FIFOVC		0x0F000000	/* FIFO valid count */
#define NET2280_EP_STAT_HBOUTPID	0x00C00000	/* high bw OUT PID */
#define NET2280_EP_STAT_TIMEOUT		0x00200000	/* time out */
#define NET2280_EP_STAT_STALLSNT	0x00100000	/* stall sent */
#define NET2280_EP_STAT_INNAKSNT	0x00080000	/* USB IN NAK Sent */
#define NET2280_EP_STAT_INACKRCV	0x00040000	/* USB IN ACK Sent */ 
#define NET2280_EP_STAT_OPNAKSNT	0x00020000	/* USB OUT NAK Sent */
#define NET2280_EP_STAT_OUTACKSNT	0x00010000	/* USB OUT ACK Sent */
#define NET2280_EP_STAT_FIFO_OVERF	0x00002000	/* USB FIFO Overflow */
#define NET2280_EP_STAT_FIFO_UNDERF	0x00001000	/* USB FIFO Underflow*/
#define NET2280_EP_STAT_FIFO_FULL	0x00000800	/* USB FIFO Full */
#define NET2280_EP_STAT_FIFO_EMPTY	0x00000400	/* USB FIFO Empty */
#define NET2280_EP_STAT_FIFO_FLUSH	0x00000200	/* USB FIFO Flush */
#define NET2280_EP_STAT_SPOD		0x00000040	/* Short Packet Out */
							/* Done Interrupt */
#define NET2280_EP_STAT_SPT		0x00000020	/* Short Packet */
							/* Transmitted Intpt */
#define NET2280_EP_STAT_NAKOUT		0x00000010	/* NAK OUT Packets */
#define NET2280_EP_STAT_DPR		0x00000008	/* Data Packet */
							/* Received Interrupt */
#define NET2280_EP_STAT_DPT		0x00000004	/* Data Packet */
							/* Trnasmitted Intpt */
#define NET2280_EP_STAT_DOPT		0x00000002	/* Data OUT Token Int */
#define NET2280_EP_STAT_DIT		0x00000001	/* Data IN Toke Int */

#define NET2280_EP_CFG_REG_MASK		0x0007078F	/* EP_CFG: Mask Value */
#define NET2280_EP_CFG_EBC		0x00070000	/* EP_CFG: */
							/* Ept byte count */
#define NET2280_EP_CFG_ENABLE		0x00000400	/* EP_CFG: endpt enable*/
#define NET2280_EP_CFG_TYPE_INT		0x00000300	/* EP_CFG: interrupt */
							/* endpt type */
#define NET2280_EP_CFG_TYPE_BULK	0x00000200	/* EP_CFG: bulk endpt */
#define NET2280_EP_CFG_TYPE_ISO		0x00000100	/* EP_CFG: iso endpt */
#define NET2280_EP_CFG_TYPE_MASK        0x00000300	/* EP_CFG: Ept type */
#define NET2280_EP_CFG_DIRECTION	0x00000080	/* EP_CFG: Ept dir */
#define NET2280_EP_CFG_NUMBER		0x0000000F	/* EP_CFG: Ept no */
#define NET2280_EP_CFG_DIR_SHIFT        7               /* EP_CFG: dir shift */
#define NET2280_EP_CFG_TYPE_SHIFT       8               /* EP_CFG: type shift */
#define NET2280_EP_CFG_BYTE_CNT_SHIFT   16

/* Endpoint response register - bits are cleared on 0:7 and set on 8:15 */

#define NET2280_EP_RSP_NAKOUT		0x00000080
#define NET2280_EP_RSP_HIDSTAT		0x00000040
#define NET2280_EP_RSP_FCRCERR		0x00000020
#define NET2280_EP_RSP_INTMODE		0x00000010
#define NET2280_EP_RSP_CSPH		0x00000008	/* ctrl stat ph. h/s */
#define NET2280_EP_RSP_NAKOUTMOD	0x00000004
#define NET2280_EP_RSP_TOGGLE		0x00000002
#define NET2280_EP_RSP_STALL		0x00000001	/* endpoint halt */
#define NET2280_EP_RSP_SET(x)		(x << 8)
#define NET2280_EP_RSP_CLEAR(x)		(x)

/* Endpoint Interrupts */
#define NET2280_EP_IRQENB_SPOD		0x00000040	/* short pkt out done */
#define NET2280_EP_IRQENB_SPT		0x00000020	/* short pkt trans. */
#define NET2280_EP_IRQENB_DPR		0x00000008	/* data pkt recv'd */
#define NET2280_EP_IRQENB_DPT		0x00000004	/* data pkt trans. */
#define NET2280_EP_IRQENB_DOPT		0x00000002	/* data out/ping token*/
#define NET2280_EP_IRQENB_DIT		0x00000001	/* data in token */
#define NET2280_EP_IRQENB_DEFAULT	(NET2280_EP_IRQENB_SPOD | \
					NET2280_EP_IRQENB_SPT | \
					NET2280_EP_IRQENB_DPR | \
					NET2280_EP_IRQENB_DPT | \
					NET2280_EP_IRQENB_DOPT | \
					NET2280_EP_IRQENB_DIT)
#define NET2280_EP_IRQEBN_MASK          0x7F					

/* NET 2280 endpoints */

#define NET2280_NUM_ENDPOINTS		8		/* 6 generic endpoint */
		    					/* 2 control endpoint */						  	
							/* should be reported */
							/* to HAL */
/* NET 2280 DMA channels */

#define NET2280_DMA_CHANS		4    

#define NET2280_DMA_ENPT_MASK           0xF

/* FIFO Configurations */

#define NET2280_FIFOCTL_CFG0		0		/* configuration 0 */
#define NET2280_FIFOCTL_CFG1		1		/* configuration 1 */
#define NET2280_FIFOCTL_CFG2		2		/* configuration 2 */

#define NET2280_FIFOCTL_CFG_MASK	0x03		/* Fifo config mask */

/* Maximum Packet Size */
#define NET2280_MAXPSIZE_8		0x0008
#define NET2280_MAXPSIZE_16		0x0010
#define NET2280_MAXPSIZE_32		0x0020
#define NET2280_MAXPSIZE_64		0x0040
#define NET2280_MAXPSIZE_128		0x0080
#define NET2280_MAXPSIZE_256		0x0100
#define NET2280_MAXPSIZE_512		0x0200
#define NET2280_MAXPSIZE_1024		0x0400

/* Definitions for number of transactions per frame */
#define NET2280_NTRANS_1       0x0  /* 1 packet per microframe */
#define NET2280_NTRANS_2       0x1  /* 2 packets per microframe */
#define NET2280_NTRANS_3       0x2  /* 3 packet per microframe */
#define NET2280_NTRANS_SHIFT   11

/* Device product / vendor information */
#define NET2280_PRODVENDID_PROD_MASK	0xFFFF0000
#define NET2280_PROD_ID			0x2280
#define NET2280_PRODID_SHIFT            16

/* Macros for reading from and writing to the net2280 registers */


#define NET2280_CFG_READ(pTarget,offset) \
	TO_LITTLEL(*(UINT32 *)(pTarget->ioBase[0] + offset))

#define NET2280_8051_READ(pTarget,offset) \
	TO_LITTLEL(*(UINT32 *)(pTarget->ioBase[1] + offset))

#define NET2280_FIFO_READ(pTarget,offset) \
	TO_LITTLEL(*(UINT32 *)(pTarget->ioBase[2] + offset))

#define NET2280_CFG_WRITE(pTarget,offset,value) \
	(*(UINT32 *)(pTarget->ioBase[0] + offset) = FROM_LITTLEL(value))

#define NET2280_8051_WRITE(pTarget,offset, value) \
	(*(UINT32 *)(pTarget->ioBase[1] + offset) = FROM_LITTLEL(value))

#define NET2280_FIFO_WRITE(pTarget,offset,value) \
	(*(UINT32 *)(pTarget->ioBase[2] + offset) = FROM_LITTLEL(value))

#ifdef	__cplusplus
}
#endif

#endif	/* __INCusbNet2280h */