usbnet2280.h

vxworks 6.x 的全部头文件

/* usbNET2280.h - Definitions for NetChip NET 2280 USB target controller */

/* Copyright 2004 Wind River Systems, Inc. */

/*
Modification history
--------------------
01g,30sep04,pdg  Removed the endianness macros and function calls for register
                 reads and writes
01f,29sep04,ami  Changes related to Mips Testing
01e,20sep04,ami  NET2280 tested in High Speed
01d,17sep04,ami  After Control, Interrupt IN and Bulk OUT Testing
01c,08sep04,ami	 Code Review Incorporated 	
01b,03sep04,ami	 Design Changes	
01a,29jun04,pmr  written.
*/

/*
DESCRIPTION

Defines constants related to the NetChip NET 2280 USB device (target) IC.
*/

#ifndef __INCusbNet2280h
#define __INCusbNet2280h

#ifdef	__cplusplus
extern "C" {
#endif

/* includes */
#include "usb/usbPciLib.h"
#include "cacheLib.h"

/* defines */

/* Endpoint Indices */

#define NET2280_ENDPT_0_OUT   		0x0	/* Endpoint 0 OUT */
#define NET2280_ENDPT_A			0x1	/* Endpoint A */
#define NET2280_ENDPT_B			0x2	/* Endpoint B */
#define NET2280_ENDPT_C			0x3	/* Endpoint C */
#define NET2280_ENDPT_D			0x4	/* Endpoint D */
#define NET2280_ENDPT_E			0x5	/* Endpoint E */
#define NET2280_ENDPT_F			0x6	/* Endpoint F */
#define NET2280_ENDPT_0_IN              0x7     /* Endpoint 0 IN */

#define NET2280_ENDPT_CFGOUT		0xA	/* Endpoint CFG OUT */
#define NET2280_ENDPT_CFGIN		0xB	/* Endpoint CFG IN */
#define NET2280_ENDPT_PCIOUT		0xC	/* Endpoint PCI OUT */
#define NET2280_ENDPT_PCIIN		0xD	/* Endpoint PCI IN */
#define NET2280_ENDPT_STATIN		0xF	/* ENDpoint STATIN */


/* Main Control Registers */

#define NET2280_DEVINIT_REG		0x00	/* Device Initialization */
#define NET2280_EECTL_REG		0x04	/* EEPROM Control */
#define NET2280_EECLKFREQ_REG		0x08	/* EEPROM Clock Frequency */
#define NET2280_PCIIRQENB0_REG		0x10/* PCI Interrupt Request Enable 0*/
#define NET2280_PCIIRQENB1_REG		0x14/* PCI Interrupt Request Enable 1*/
#define NET2280_CPUIRQENB0_REG		0x18/* CPU Interrupt Request Enable 0*/
#define NET2280_CPUIRQENB1_REG		0x1C/* CPU Interrupt Request Enable 1*/
#define NET2280_USBIRQENB1_REG		0x24/* USB Interrupt Request Enable 1*/
#define NET2280_IRQSTAT0_REG		0x28	/* Interrupt Request Status 0*/	
#define NET2280_IRQSTAT1_REG		0x2C	/* Interrupt Request Status 1*/
#define NET2280_IDXADDR_REG		0x30	/* Index Regsiter Address */
#define NET2280_IDXDATA_REG		0x34	/* Index Register Data */
#define NET2280_FIFOCTL_REG		0x38	/* FIFO Control */
#define NET2280_MEMADDR_REG		0x40	/* FIFO Memory Diagnostic addr*/
#define NET2280_MEMDATA0_REG		0x44	/* FIFO Memory Diagnostic Data0*/
#define NET2280_MEMDATA1_REG		0x48	/* FIFO Memory Diagnostic Data1*/
#define NET2280_GPIOCTL_REG		0x50	/* General Purpose Control Reg.*/
#define NET2280_GPIOSTAT_REG		0x54	/* General Purpose Status Reg */

/* USB Control Registers */

#define NET2280_STDRSP_REG		0x80	/* Standard Response Regsiter */
#define NET2280_PRODVENDID_REG		0x84	/* Product/Vendor ID */
#define NET2280_RELNUM_REG		0x88	/* Release Number */
#define NET2280_USBCTL_REG		0x8C	/* USB Control */
#define NET2280_USBSTAT_REG		0x90	/* USB Status */
#define NET2280_XCVRDIAG_REG		0x94	/* Transceiver Mode Regsiter */
#define NET2280_SETUP0123_REG		0x98	/* Setup Bytes 0,1,2,3 */
#define NET2280_SETUP4567_REG		0x9C	/* Setup Bytes 4,5,6,7 */
#define NET2280_OURADDR_REG		0xA4	/* Address Register */
#define NET2280_OURCONFIG_REG		0xA8	/* Configuration Register */

/* PCI Control Registers */

#define NET2280_PCIMSTCTL_REG		0x100	/* PCI Master Control */
#define NET2280_PCIMSTADDR_REG		0x104	/* PCI Master Address */
#define NET2280_PCIMSTDATA_REG		0x108	/* PCI Master Data */
#define NET2280_PCIMSTSTAT_REG		0x10C	/* PCI Master Status */

/* DMA  Registers */

#define NET2280_DMACTL_OFFSET(x)	\
	(NET2280_DMA_REG_BASE(x) + 0x00)	/* DMA Control */
#define NET2280_DMASTAT_OFFSET(x)		\
	(NET2280_DMA_REG_BASE(x) + 0x04)	/* DMA Status */
#define NET2280_DMACOUNT_OFFSET(x)		\
	(NET2280_DMA_REG_BASE(x) + 0x10)	/* DMA Count */
#define NET2280_DMAADDR_OFFSET(x)		\
	(NET2280_DMA_REG_BASE(x) + 0x14)	/* DMA Address */
#define NET2280_DMADESC_OFFSET(x)		\
	(NET2280_DMA_REG_BASE(x) + 0x18)	/* DMA Descriptor */

/* 
 * DMA channels are permanently associated with endpoints.  The driver will
 * select the DMA channel based upon which endpoint is being used. The base
 * address should be added with the offset of the register 
 */

#define NET2280_DMA_REG_BASE(x)		(0x160 + 0x20 * x)

/* Dedicated Endpoint Registers */

#define NET2280_DEP_CFG_OFFSET		0x0	/* DEP_CFG Offset */
#define NET2280_DEP_RSP_OFFSET		0x4	/* DEP_RES Offset */

#define NET2280_DEP_CFGOUT_REG_BASE	0x200	/* CFG OUT Base */
#define NET2280_DEP_CFGIN_REG_BASE	0x210	/* CFG IN Base */
#define NET2280_DEP_PCIOUT_REG_BASE	0x220	/* PCI OUT Base */
#define NET2280_DEP_PCIIN_REG_BASE	0x230	/* PCI IN Base */
#define NET2280_DEP_STATIN_REG_BASE	0x240	/* STAT IN Base */

/* Configurable Endpoint / FIFO Registers */

#define NET2280_EP_CFG_OFFSET(x)	\
       	(NET2280_EP_REG_BASE(x) + 0x00)	/* endpt config. offset */ 
#define NET2280_EP_RSP_OFFSET(x)		\
       	(NET2280_EP_REG_BASE(x) + 0x04)	/* endpt response offset */
#define NET2280_EP_IRQENB_OFFSET(x)	\
       	(NET2280_EP_REG_BASE(x) + 0x08)	/* endpt intr enable offset */
#define NET2280_EP_STAT_OFFSET(x)		\
       	(NET2280_EP_REG_BASE(x) + 0x0C)	/* endpt status offset */
#define NET2280_EP_AVAIL_OFFSET(x)		\
       	(NET2280_EP_REG_BASE(x) + 0x10)	/* endpt avail offset */
#define NET2280_EP_DATA_OFFSET(x)		\
       	(NET2280_EP_REG_BASE(x) + 0x14)	/* endpt data offset */

/* 
 * Every endpoint has a seperate set of register. Add the endpoint register 
 * offset with  the base address 
 */

#define NET2280_EP_REG_BASE(x)		(0x300 + 0x20 * x)

/* Indexed Registers */

#define NET2280_DIAG_IDX		0x00	/* Diagnostic Control Reg */
#define NET2280_PKTLEN_IDX		0x01	/* Packet Length Reg */
#define NET2280_FRAME_IDX		0x02	/* Frame Counter Reg */
#define NET2280_CHIPREV_IDX		0x03	/* Chip Revision Reg */
#define NET2280_HS_MAXPOWER_IDX		0x06	/* HS Max Power Reg */
#define NET2280_FS_MAXPOWER_IDX		0x07	/* FS Max Power Reg */
#define NET2280_HS_INTPOLL_RATE_IDX	0x08	/* HS Int Polling Rate */
#define NET2280_FS_INTPOLL_RATE_IDX	0x09	/* FS Int Poling Rate */
#define NET2280_HS_NAK_RATE_IDX		0x0A	/* HS NAK Rate Reg */
#define NET2280_SCRATCH_IDX		0x0B	/* Scratch Pad */

#define NET2280_EP_X_HS_MAXPKT_IDX(x)   (0x10 + x * 0x10)
#define NET2280_EP_X_FS_MAXPKT_IDX(x)   (0x11 + x * 0x10)

/* Bits & Masks */

#define NET2280_OURADDR_REG_MASK	0x7F	/* OURADDR: Address Mask */
#define NET2280_OURADDR_REG_FI		0x80	/* OURADDR: Force Immediate */

#define NET2280_USBSTAT_REG_MASK	0xF0	/* USBSTAT: Register Mask */
#define NET2280_USBSTAT_REG_GENDEVREMWKUP	0x10	/* USBSTAT: */
							/* Generate Remote */
							/* Wakeup */
#define NET2280_USBSTAT_REG_GENRES	0x20	/* USBSTAT: Generate Resume */
#define NET2280_USBSTAT_FS		0x40	/* USBSTAT: Full Speed */
#define NET2280_USBSTAT_HS		0x80  	/* USBSTAT: High Speed */


#define NET2280_USBCTL_REG_MASK		0x00FF3EFF  /* USBCTL: Reg Mask */			
#define NET2280_USBCTL_REG_SERNUMID	0x00FF0000  /* USBCTL: Serial */
						    /* Index Number */
#define NET2280_USBCTL_REG_PRODIDEN	0x00002000  /* USBCTL: Prod ID */
#define NET2280_USBCTL_REG_VENDIDEN	0x00001000  /* USBCTL: Vend ID */
#define NET2280_USBCTL_REG_RPWE		0x00000800  /* USBCTL: Rem WKUP */
#define NET2280_USBCTL_REG_VBUSPIN	0x00000400  /* USBCTL: VBUS */
#define NET2280_USBCTL_REG_SUSPIMM	0x00000080  /* USBCTL: SUSP IMMD */
#define NET2280_USBCTL_REG_SPUD		0x00000040  /* USBCTL: Self Powered*/
#define NET2280_USBCTL_REG_RWS		0x00000020  /* USBCTL: Rem WKUP Sup */
#define NET2280_USBCTL_REG_USBDE	0x00000008  /* USBCTL: USB Detect Enb */
#define NET2280_USBCTL_REG_DRWUE	0x00000002  /* USBCTL: Dev Remote */ 
                                                    /* Wake Enable*/	
#define NET2280_USBCTL_REG_SPWRSTAT	0x00000001  /* USBCTL: Self Powered */
						    /* Status */		

#define NET2280_FRAME_REG_MASK		0x7FF	/* FRAME: Frame Mask */

#define NET2280_DEVINIT_REG_MASK	0xFFF	/* DEVINIT: Reg Mask */
#define NET2280_DEVINIT_REG_FRC_PCI_RESET 0x080	/* DEVINIT: Force PCI Reset */
#define NET2280_DEVINIT_REG_PCI_ID	0x040	/* DEVINIT: PCI ID */
#define NET2280_DEVINIT_PCIEN		0x020	/* DEVINIT: PCI Enable */
#define NET2280_DEVINIT_FIFO_RESET	0x010	/* DEVINIT: FIFO Reset */
#define NET2280_DEVINIT_CFG_RESET	0x008	/* DEVINIT: CFG Reset */
#define NET2280_DEVINIT_PCI_RESET	0x004	/* DEVINIT: PCI Reset */
#define NET2280_DEVINIT_USB_RESET	0x002	/* DEVINIT: USB Reset */
#define NET2280_DEVINIT_8051_RESET	0x001	/* DEVINIT: 851 Reset */
#define NET2280_DEVINIT_FULL_RESET	(NET2280_DEVINIT_FIFO_RESET | \
					 NET2280_DEVINIT_USB_RESET | \
					 NET2280_DEVINIT_8051_RESET)
#define NET2280_DEVINIT_CLK_FREQ        (8 << 8)/* DEVINIT: CLK FREQUENCY */  

/* Interrupt enable registers (CPU, PCI, & USB) */

#define NET2280_XIRQENB0_SETUP		0x00000080