vmechip.h

vxworks 6.x 的全部头文件

/* vmechip.h - Motorola MVME6000 VMEbus Interface Controller */

/* Copyright 1991-1992 Wind River Systems, Inc. */
/*
modification history
--------------------
01f,29sep98,fle  doc : made it refgen parsable
01e,22sep92,rrr  added support for c++
01d,03jun92,ccc  added a few more constants.
01c,26may92,rrr  the tree shuffle
01b,02jan92,caf  fixed GLOBAL_0 bits. changed copyright notice.
01a,19dec91,caf  written.
*/

#ifdef	DOC
#define INCvmechiph
#endif	/* DOC */

#ifndef __INCvmechiph
#define __INCvmechiph

#ifdef __cplusplus
extern "C" {
#endif

/*
This file contains constants for the Motorola MVME6000 VMEbus Interface.
The macro VMECHIP_BASE_ADRS must be defined when using local bus addresses
defined in this header.  The macro GCSR_BUS_BASE_ADRS must be defined when
using VMEbus addresses defined in this header.

The following standards have been adopted in the creation of this file.

Registers in the LCSR have the prefix "LCSR".

Registers in the GCSR have the prefix "GCSR" when addressed locally and the
prefix "GCSR_BUS" when addressed from the VMEbus.  The bit definitions are
shared.

The registers are listed in ascending (numerical) order; the definitions
for each register start with a header, e.g.:

 Register                Register Register Register
 Mnemonic                Number   Address  Name
    |                        |       |       |
    v                        v       v       v
*************************************************************************
* SYS_CONF                  0x00    0x01    system controller config    *
*************************************************************************

In cases where a number of registers have the same definitions, the
header looks like this:

*************************************************************************
* GP_CSR_0                  0x13    0x27    general purpose CSR 0       *
* to                                                                    *
* GP_CSR_4                  0x17    0x2f    general purpose CSR 4       *
*************************************************************************

The format of the definitions is as follows.  The define name always
starts with the register mnemonic it is associated with.  The [7-0]
number at the end of the comment indicates the bit position to which the
the define applies.  In the definition of RQST_CONF_DWB, for example,
the 7 indicates bit 7:
                                                                      |
                                                                      v
 define RQST_CONF_DWB       0x80     * device wants bus               7 *

If the define applies to more than one bit, then the applicable bit
range is specified by two digits.  In the following example,
TMO_CONF_VBTO_2048 applies to the two bit field, bits 5-4:
                                                                      |
                                                                      v
 define TMO_CONF_VBTO_2048  0x10     * VMEbus time-out 2048 * T      54 *

If no bit field is given, then the define applies to the whole register.
*/

#ifdef	_ASMLANGUAGE
#define	CAST
#else
#define	CAST (char *)
#endif	/* _ASMLANGUAGE */

#define	VMECHIP_REG_INTERVAL            2

#ifndef	VMECHIP_ADRS    /* to permit alternative board addressing */
#define	VMECHIP_ADRS(reg) \
                (CAST (VMECHIP_BASE_ADRS + 1 + (reg * VMECHIP_REG_INTERVAL)))
#endif	/* VMECHIP_ADRS */

/*
 * Local Control and Status Register (LCSR) definitions.
 *
 * Only the local CPU can access the LCSR.
 */

#define LCSR_SYS_CONF       VMECHIP_ADRS(0x00)  /* system controller config  */
#define LCSR_RQST_CONF      VMECHIP_ADRS(0x01)  /* requester configuration   */
#define LCSR_MASTER_CONF    VMECHIP_ADRS(0x02)  /* master configuration      */
#define LCSR_SLAVE_CONF     VMECHIP_ADRS(0x03)  /* slave configuration       */
#define LCSR_TMO_CONF       VMECHIP_ADRS(0x04)  /* timer configuration       */
#define LCSR_SLAVE_AM       VMECHIP_ADRS(0x05)  /* slave address modifier    */
#define LCSR_MASTER_AM      VMECHIP_ADRS(0x06)  /* master address modifier   */
#define LCSR_INT_MASK       VMECHIP_ADRS(0x07)  /* interrupt handler mask    */
#define LCSR_UTIL_INT_MASK  VMECHIP_ADRS(0x08)  /* utility interrupt mask    */
#define LCSR_UTIL_VEC_BASE  VMECHIP_ADRS(0x09)  /* utility interrupt vector  */
#define LCSR_INT_REQ        VMECHIP_ADRS(0x0a)  /* interrupt request         */
#define LCSR_INT_STATUS_ID  VMECHIP_ADRS(0x0b)  /* status/ID                 */
#define LCSR_BERR_STATUS    VMECHIP_ADRS(0x0c)  /* bus error status          */
#define LCSR_GCSR_BASE_ADRS VMECHIP_ADRS(0x0d)  /* GCSR base address         */


/*
 * Global Control and Status Register (GCSR) definitions.
 *
 * All registers of the GCSR are accessible to both the local processor
 * and to other VMEbus masters.
 */

/* local addresses for the GCSR */

#define GCSR_GLOBAL_0       VMECHIP_ADRS(0x10)  /* global 0                  */
#define GCSR_GLOBAL_1       VMECHIP_ADRS(0x11)  /* global 1                  */
#define GCSR_BOARD_ID       VMECHIP_ADRS(0x12)  /* board ID                  */
#define GCSR_GP_CSR_0       VMECHIP_ADRS(0x13)  /* general purpose CSR 0     */
#define GCSR_GP_CSR_1       VMECHIP_ADRS(0x14)  /* general purpose CSR 1     */
#define GCSR_GP_CSR_2       VMECHIP_ADRS(0x15)  /* general purpose CSR 2     */
#define GCSR_GP_CSR_3       VMECHIP_ADRS(0x16)  /* general purpose CSR 3     */
#define GCSR_GP_CSR_4       VMECHIP_ADRS(0x17)  /* general purpose CSR 4     */

/* VMEbus addresses for the GCSR */

#define GCSR_BUS_REG_INTERVAL           2

#ifndef GCSR_BUS_ADRS   /* to permit alternative off-board addressing */
#define GCSR_BUS_ADRS(reg) \
                (CAST (GCSR_BUS_BASE_ADRS + 1 + (reg * GCSR_BUS_REG_INTERVAL)))
#endif  /* GCSR_BUS_ADRS */

#define GCSR_BUS_GLOBAL_0   GCSR_BUS_ADRS(0x00) /* global 0 on VMEbus        */
#define GCSR_BUS_GLOBAL_1   GCSR_BUS_ADRS(0x01) /* global 1 on VMEbus        */
#define GCSR_BUS_BOARD_ID   GCSR_BUS_ADRS(0x02) /* board ID on VMEbus        */
#define GCSR_BUS_GP_CSR_0   GCSR_BUS_ADRS(0x03) /* general purp. 0 on VMEbus */
#define GCSR_BUS_GP_CSR_1   GCSR_BUS_ADRS(0x04) /* general purp. 1 on VMEbus */
#define GCSR_BUS_GP_CSR_2   GCSR_BUS_ADRS(0x05) /* general purp. 2 on VMEbus */
#define GCSR_BUS_GP_CSR_3   GCSR_BUS_ADRS(0x06) /* general purp. 3 on VMEbus */
#define GCSR_BUS_GP_CSR_4   GCSR_BUS_ADRS(0x07) /* general purp. 4 on VMEbus */


/* SYS_CONF                  0x00    0x01    system controller config   */

#define SYS_CONF_SCON       0x01    /* system controller on (status)  0 */
#define SYS_CONF_SRESET     0x02    /* system reset                   1 */
#define SYS_CONF_BRDFAIL    0x04    /* board fail                     2 */
#define SYS_CONF_ROBIN      0x08    /* round robin select             3 */
#define SYS_CONF_PRIORITY   0x00    /* priority mode select           3 */

/* RQST_CONF                 0x01    0x03    requester configuration    */

#define RQST_CONF_RQLEV     0x03    /* VMEbus request level (mask)   10 */
#define RQST_CONF_RQLEV_0   0x00    /* VMEbus request level 0        10 */
#define RQST_CONF_RQLEV_1   0x01    /* VMEbus request level 1        10 */
#define RQST_CONF_RQLEV_2   0x02    /* VMEbus request level 2        10 */
#define RQST_CONF_RQLEV_3   0x03    /* VMEbus request level 3        10 */

#define RQST_CONF_RNEVER    0x08    /* release never                  3 */