dga001vme.h

vxworks 6.x 的全部头文件

#define CSR1_2_RQT_DIS	0x30	/* request time-out disable         5-4 */
#define CSR1_2_RQT_1023	0x20	/* request time-out 1023 usec       5-4 */
#define CSR1_2_RQT_511	0x10	/* request time-out 511 usec        5-4 */
#define CSR1_2_RQT_255	0x00	/* request time-out 255 usec        5-4 */

#define CSR1_2_RNV	0x0c	/* release never                    3-2 */
#define CSR1_2_RBC	0x08	/* release when bus clear           3-2 */
#define CSR1_2_RWD	0x04	/* release when done                3-2 */
#define CSR1_2_ROR	0x00	/* release on request               3-2 */

#define CSR1_2_BR3	0x03	/* VMEbus request level 3           1-0 */
#define CSR1_2_BR2	0x02	/* VMEbus request level 2           1-0 */
#define CSR1_2_BR1	0x01	/* VMEbus request level 1           1-0 */
#define CSR1_2_BR0	0x00	/* VMEbus request level 0           1-0 */

/*************************************************************************
* CSR1_3                0x01    0x07    VMEbus master control            *
*************************************************************************/

#define CSR1_3_RMC	0x80	/* read-modify-write cycle            7 */

#define CSR1_3_AAMEN	0x40	/* addess modifier code enable        6 */
#define CSR1_3_AAMDIS	0x00	/* addess modifier code disable       6 */
#define CSR1_3_AAM	0x3f	/* addess modifier code (mask)      5-0 */

/*************************************************************************
* CSR2_0                0x02    0x08    unused                           *
* to                                                                     *
* CSR3_1                0x03    0x0d    unused                           *
*************************************************************************/

/*************************************************************************
* CSR3_2                0x03    0x0e    interface register address       *
*************************************************************************/

#define CSR3_2_IFRA_H	0xff	/* interface register addess (mask) 7-0 */

/*************************************************************************
* CSR3_3                0x03    0x0f    interface register address       *
*************************************************************************/

#define CSR3_3_IFRA_L	0xf0	/* interface register addess (mask) 7-4 */

#define CSR3_3_IFRSUP	0x02	/* respond to supervisor              1 */
#define CSR3_3_IFRUSR	0x01	/* respond to user                    0 */

/*************************************************************************
* CSR4_01               0x04    0x10    slave address 0                  *
*************************************************************************/

#define CSR4_01_SL0A	0xffff	/* slave addess 0 (mask)           15-0 */

/*************************************************************************
* CSR4_23               0x04    0x12    address mask 0                   *
*************************************************************************/

#define CSR4_23_AM0A	0xffff	/* address mask 0 (mask)           15-0 */

/*************************************************************************
* CSR5_01               0x05    0x14    mapping address 0                *
*************************************************************************/

#define CSR5_01_MP0A	0xffff	/* mapping address 0 (mask)        15-0 */

/*************************************************************************
* CSR5_23               0x05    0x16    slave control 0                  *
*************************************************************************/

#define CSR5_23_A32EN0	0x0020	/* respond to extended                5 */
#define CSR5_23_A24EN0	0x0010	/* respond to standard                4 */
#define CSR5_23_SUPER0	0x0008	/* respond to supervisor              3 */
#define CSR5_23_USER0	0x0004	/* respond to user                    2 */
#define CSR5_23_PRGRM0	0x0002	/* respond to program                 1 */
#define CSR5_23_DATA0	0x0001	/* respond to data                    0 */

/*************************************************************************
* CSR6_01               0x06    0x18    save address 1                   *
*************************************************************************/

#define CSR6_01_SL0A	0xffff	/* slave addess 1 (mask)           15-0 */

/*************************************************************************
* CSR6_23               0x06    0x1a    address mask 1                   *
*************************************************************************/

#define CSR6_23_AM0A	0xffff	/* address mask 1 (mask)           15-0 */

/*************************************************************************
* CSR7_01               0x07    0x1c    mapping addess 1                 *
*************************************************************************/

#define CSR7_01_MP0A	0xffff	/* mapping address 1 (mask)        15-0 */

/*************************************************************************
* CSR7_23               0x07    0x1e    slave control 1                  *
*************************************************************************/

#define CSR7_23_A32EN0	0x0020	/* respond to extended                5 */
#define CSR7_23_A24EN0	0x0010	/* respond to standard                4 */
#define CSR7_23_SUPER0	0x0008	/* respond to supervisor              3 */
#define CSR7_23_USER0	0x0004	/* respond to user                    2 */
#define CSR7_23_PRGRM0	0x0002	/* respond to program                 1 */
#define CSR7_23_DATA0	0x0001	/* respond to data                    0 */

/*************************************************************************
* CSR12                 0x0c    0x30    tick timer 0 control             *
*************************************************************************/

#define CSR12_TT0CEN	0x80000000	/* tick timer 0 enable          */

/*************************************************************************
* CSR13                 0x0d    0x34    tick timer 0 counter             *
*************************************************************************/

#define CSR13_TT0OCL	0x80000000	/* overflow counter clear       */

/*************************************************************************
* CSR14                 0x0e    0x38    tick timer 1 control             *
*************************************************************************/

#define CSR14_TT1CEN	0x80000000	/* tick timer 1 enable          */

/*************************************************************************
* CSR15                 0x0f    0x3c    tick timer 1 counter             *
*************************************************************************/

#define CSR15_TT1OCL	0x80000000	/* overflow counter clear       */

/*************************************************************************
* CSR16                 0x10    0x40    watchdog timer control           *
*************************************************************************/

#define CSR16_WDTCEN	0x80000000	/* watchdog timer enable        */
#define	CSR16_WDTSFE	0x40000000	/* watchdog timer SYSFAIL enable*/

/*************************************************************************
* CSR17                 0x11    0x44    watchdog timer counter           *
*************************************************************************/

#define CSR17_WDTCLR	0x80000000	/* watchdog timer counter clear */
#define	CSR17_WDTOUT	0x01000000	/* watchdog timeout (status)    */

/*************************************************************************
* CSR18_1               0x12	0x49	interrupt sense mode control	 *
*************************************************************************/

#define	CSR18_1_ACFLVL	0x80	/* ACFAIL  int level(1)/edge(0) sense 7 */
#define	CSR18_1_ABTLVL	0x40	/* ABORT   int level(1)/edge(0) sense 6 */
#define	CSR18_1_SFLVL	0x20	/* SYSFAIL int level(1)/edge(0) sense 5 */

/*************************************************************************
* CSR20                 0x14    0x50    interrupt status                 *
*************************************************************************/

#define CSR20_ACFIRQ	0x80000000	/* ACFAIL interrupt        31 */
#define CSR20_ABTIRQ	0x40000000	/* ABORT  interrupt        30 */
#define CSR20_SFIRQ	0x20000000	/* SYSFAIL interrupt       29 */
#define CSR20_BERIRQ	0x10000000	/* BERR interrupt          28 */
#define CSR20_IAKIRQ	0x08000000	/* IAK interrupt           27 */
#define CSR20_SRQIRQ	0x04000000	/* SRQ interrupt           26 */
#define CSR20_SAKIRQ	0x02000000	/* SAKF interrupt          25 */

#define CSR20_GP7IRQ	0x00800000	/* GP7 interrupt           23 */
#define CSR20_DMAIRQ	0x00400000	/* DMA interrupt           22 */
#define CSR20_TT1IRQ	0x00200000	/* TT1 interrupt           21 */
#define CSR20_TT0IRQ	0x00100000	/* TT0 interrupt           20 */
#define CSR20_GP3IRQ	0x00080000	/* GP3 interrupt           19 */
#define CSR20_GP2IRQ	0x00040000	/* GP2 interrupt           18 */
#define CSR20_GP1IRQ	0x00020000	/* GP1 interrupt           17 */
#define CSR20_GP0IRQ	0x00010000	/* GP0 interrupt           16 */

#define CSR20_SWIRQ7	0x00008000	/* SWIRQ7 interrupt        15 */
#define CSR20_SWIRQ6	0x00004000	/* SWIRQ6 interrupt        14 */
#define CSR20_SWIRQ5	0x00002000	/* SWIRQ5 interrupt        13 */
#define CSR20_SWIRQ4	0x00001000	/* SWIRQ4 interrupt        12 */
#define CSR20_SWIRQ3	0x00000800	/* SWIRQ3 interrupt        11 */
#define CSR20_SWIRQ2	0x00000400	/* SWIRQ2 interrupt        10 */
#define CSR20_SWIRQ1	0x00000200	/* SWIRQ1 interrupt        9 */
#define CSR20_SWIRQ0	0x00000100	/* SWIRQ0 interrupt        8 */

#define CSR20_VMIRQ7	0x00000080	/* VMIRQ7 interrupt        7 */
#define CSR20_VMIRQ6	0x00000040	/* VMIRQ7 interrupt        6 */
#define CSR20_VMIRQ5	0x00000020	/* VMIRQ7 interrupt        5 */
#define CSR20_VMIRQ4	0x00000010	/* VMIRQ4 interrupt        4 */
#define CSR20_VMIRQ3	0x00000008	/* VMIRQ3 interrupt        3 */
#define CSR20_VMIRQ2	0x00000004	/* VMIRQ2 interrupt        2 */
#define CSR20_VMIRQ1	0x00000002	/* VMIRQ1 interrupt        1 */

/*************************************************************************
* CSR21                 0x14    0x50    interrupt enable                 *
*************************************************************************/

#define CSR21_ACFIEN	0x80000000	/* ACFAIL interrupt           31 */
#define CSR21_ABTIEN	0x40000000	/* ABORT  interrupt           30 */
#define CSR21_SFIEN	0x20000000	/* SYSFAIL interrupt          29 */
#define CSR21_BERIEN	0x10000000	/* BERR interrupt             28 */
#define CSR21_IAKIEN	0x08000000	/* IAK interrupt              27 */
#define CSR21_SRQIEN	0x04000000	/* SRQ interrupt              26 */
#define CSR21_SAKIEN	0x02000000	/* SAKF interrupt             25 */

#define CSR21_GP7IEN	0x00800000	/* GP7 interrupt              23 */
#define CSR21_DMAIEN	0x00400000	/* DMA interrupt              22 */
#define CSR21_TT1IEN	0x00200000	/* TT1 interrupt              21 */
#define CSR21_TT0IEN	0x00100000	/* TT0 interrupt              20 */
#define CSR21_GP3IEN	0x00080000	/* GP3 interrupt              19 */
#define CSR21_GP2IEN	0x00040000	/* GP2 interrupt              18 */
#define CSR21_GP1IEN	0x00020000	/* GP1 interrupt              17 */
#define CSR21_GP0IEN	0x00010000	/* GP0 interrupt              16 */

#define CSR21_SWIEN7	0x00008000	/* SWIRQ7 interrupt           15 */
#define CSR21_SWIEN6	0x00004000	/* SWIRQ6 interrupt           14 */
#define CSR21_SWIEN5	0x00002000	/* SWIRQ5 interrupt           13 */
#define CSR21_SWIEN4	0x00001000	/* SWIRQ4 interrupt           12 */
#define CSR21_SWIEN3	0x00000800	/* SWIRQ3 interrupt           11 */
#define CSR21_SWIEN2	0x00000400	/* SWIRQ2 interrupt           10 */
#define CSR21_SWIEN1	0x00000200	/* SWIRQ1 interrupt           9 */
#define CSR21_SWIEN0	0x00000100	/* SWIRQ0 interrupt           8 */

#define CSR21_VMIEN7	0x00000080	/* VMIRQ7 interrupt           7 */
#define CSR21_VMIEN6	0x00000040	/* VMIRQ7 interrupt           6 */
#define CSR21_VMIEN5	0x00000020	/* VMIRQ7 interrupt           5 */
#define CSR21_VMIEN4	0x00000010	/* VMIRQ4 interrupt           4 */
#define CSR21_VMIEN3	0x00000008	/* VMIRQ3 interrupt           3 */
#define CSR21_VMIEN2	0x00000004	/* VMIRQ2 interrupt           2 */
#define CSR21_VMIEN1	0x00000002	/* VMIRQ1 interrupt           1 */

/*************************************************************************
* CSR23                 0x16    0x5c    interrupt clear                  *
*************************************************************************/

#define CSR23_ACFICL	0x80000000	/* ACFAIL clear              31 */
#define CSR23_ABTICL	0x40000000	/* ABORT  clear              30 */
#define CSR23_SFICL	0x20000000	/* SYSFAIL clear             29 */
#define CSR23_IAKICL	0x08000000	/* IAK clear                 27 */
#define CSR23_SRQICL	0x04000000	/* SRQ clear                 26 */
#define CSR23_SAKICL	0x02000000	/* SAK clear                 25 */
#define CSR23_DMAICL	0x00400000	/* DMA clear                 22 */
#define CSR23_TT1ICL	0x00200000	/* TT1 clear                 21 */
#define CSR23_TT0ICL	0x00100000	/* TT0 clear                 20 */

/*************************************************************************
* IFR0                  0x1c    0x70    interface register 0             *
*************************************************************************/

#define IFR0_SRQF    0x80000000	/* SRQ clear                         31 */

/*************************************************************************
* IFR1                  0x1d    0x74    interface register 1             *
*************************************************************************/

#define IFR1_SAKF    0x80000000	/* SAK clear                         31 */

/*************************************************************************
* IFR3                  0x1f    0x7c    interface register 3             *
*************************************************************************/

#define IFR3_SWREN   0x80000000	/* software reset enable bit         31 */

#ifdef __cplusplus
}
#endif

#endif /* INCdga001Vmeh */