📄 dga001vme.h
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/* dga001Vme.h - Densan DGA-001 VMEbus Interface Controller *//* Copyright 1994-1997 Wind River Systems, Inc. */#include "copyright_wrs.h"/*modification history--------------------01l,12jul97,hk renamed as dga001Vme.h from drv/multi/dga001.h.01k,15jan96,hk added support for DVE-SH7043.01j,10nov95,hk changed CSR to DGA_CSR.01i,09nov95,hk fixed CSR1_1_RRS, but not used. did some code reviewing.01h,04jul95,hk modified some macro names.01g,07jun95,hk changed CSR20/CSR21 bit defs. copyright to '95.01f,15dec94,sa wrote CSR13_0, CSR15_0, CSR16_0, CSR17, IFR0, IFR1, IFR3.01e,14nov94,hk wrote CSR18_1.01d,09nov94,sa write CSR12, CSR14 and CSR23.01c,19oct94,sa write CSR19 to CSR2101b,08sep94,sa write to CSR701a,07sep94,sa derived from 01e of vmechip.h.*/#ifdef DOC#define INCdga001Vmeh#endif /* DOC */#ifndef __INCdga001Vmeh#define __INCdga001Vmeh#ifdef __cplusplusextern "C" {#endif/*This file contains constants for the Densan DGA-001 VMEbus Interface.The macro DGA001_BASE_ADRS must be defined when using local bus addressesdefined in this header. The macro IFR_BUS_BASE_ADRS must be defined whenusing VMEbus addresses defined in this header.The following standards have been adopted in the creation of this file.Registers in the CSR have the prefix "DGA_CSR". And "DGA_CSR0_0" means mostlow address of CSR0 register.Registers in the IFR have the prefix "DGA_IFR" when addressed locally andthe prefix "IFR_BUS" when addressed from the VMEbus. The bit definitionsare shared.The registers are listed in ascending (numerical) order; the definitionsfor each register start with a header, e.g.: Register Register Register Register Mnemonic Number Address Name | | | | v v v v/@************************************************************************ CSR0_0 0x00 0x00 local bus control and status************************************************************************@/The format of the definitions is as follows. The define name alwaysstarts with the register mnemonic it is associated with. The [7-0]number at the end of the comment indicates the bit position to which thethe define applies. In the definition of PURSTF, for example, the 7 indicates bit 7: | v#define CSR1_0_PURSTF 0x80 /@ power-up status bit 7 @/If the define applies to more than one bit, then the applicable bitrange is specified by two digits. In the following example,CSR0_LBT applies to the two bit field, bits 5-4: | v#define CSR0_0_LBT 0x10 /@ local bus time-out (mask) 54 @/If no bit field is given, then the define applies to the whole register.*/#define DGA001_LONG_ADRS(offset) \ ((volatile UINT32 *)(DGA001_BASE_ADRS + offset))#if defined(TARGET_DVE7604) || defined(TARGET_DVE7043)#define DGA001_BYTE_ADRS(offset) \ ((volatile UINT8 *)(DGA001_BASE_ADRS + DGA001_BYTE_ACCESS_OFFSET + offset))#else#define DGA001_BYTE_ADRS(offset) \ ((volatile UINT8 *)(DGA001_BASE_ADRS + offset))#endif /* TARGET_DVE7604 *//* * Control and Status Register (CSR) definitions. * * only the local CPU can access the LCSR. */#define DGA_CSR0 DGA001_LONG_ADRS(0x00)#define DGA_CSR0_0 DGA001_BYTE_ADRS(0x00)#define DGA_CSR0_1 DGA001_BYTE_ADRS(0x01)#define DGA_CSR0_2 DGA001_BYTE_ADRS(0x02)#define DGA_CSR0_3 DGA001_BYTE_ADRS(0x03)#define DGA_CSR1 DGA001_LONG_ADRS(0x04)#define DGA_CSR1_0 DGA001_BYTE_ADRS(0x04)#define DGA_CSR1_1 DGA001_BYTE_ADRS(0x05)#define DGA_CSR1_2 DGA001_BYTE_ADRS(0x06)#define DGA_CSR1_3 DGA001_BYTE_ADRS(0x07)#define DGA_CSR2 DGA001_LONG_ADRS(0x08)#define DGA_CSR2_0 DGA001_BYTE_ADRS(0x08)#define DGA_CSR2_1 DGA001_BYTE_ADRS(0x09)#define DGA_CSR2_2 DGA001_BYTE_ADRS(0x0a)#define DGA_CSR2_3 DGA001_BYTE_ADRS(0x0b)#define DGA_CSR3 DGA001_LONG_ADRS(0x0c)#define DGA_CSR3_0 DGA001_BYTE_ADRS(0x0c)#define DGA_CSR3_1 DGA001_BYTE_ADRS(0x0d)#define DGA_CSR3_2 DGA001_BYTE_ADRS(0x0e)#define DGA_CSR3_3 DGA001_BYTE_ADRS(0x0f)#define DGA_CSR4 DGA001_LONG_ADRS(0x10)#define DGA_CSR4_0 DGA001_BYTE_ADRS(0x10)#define DGA_CSR4_1 DGA001_BYTE_ADRS(0x11)#define DGA_CSR4_2 DGA001_BYTE_ADRS(0x12)#define DGA_CSR4_3 DGA001_BYTE_ADRS(0x13)#define DGA_CSR5 DGA001_LONG_ADRS(0x14)#define DGA_CSR5_0 DGA001_BYTE_ADRS(0x14)#define DGA_CSR5_1 DGA001_BYTE_ADRS(0x15)#define DGA_CSR5_2 DGA001_BYTE_ADRS(0x16)#define DGA_CSR5_3 DGA001_BYTE_ADRS(0x17)#define DGA_CSR6 DGA001_LONG_ADRS(0x18)#define DGA_CSR6_0 DGA001_BYTE_ADRS(0x18)#define DGA_CSR6_1 DGA001_BYTE_ADRS(0x19)#define DGA_CSR6_2 DGA001_BYTE_ADRS(0x1a)#define DGA_CSR6_3 DGA001_BYTE_ADRS(0x1b)#define DGA_CSR7 DGA001_LONG_ADRS(0x1c)#define DGA_CSR7_0 DGA001_BYTE_ADRS(0x1c)#define DGA_CSR7_1 DGA001_BYTE_ADRS(0x1d)#define DGA_CSR7_2 DGA001_BYTE_ADRS(0x1e)#define DGA_CSR7_3 DGA001_BYTE_ADRS(0x1f)#define DGA_CSR8 DGA001_LONG_ADRS(0x21)#define DGA_CSR9 DGA001_LONG_ADRS(0x24)#define DGA_CSR10 DGA001_LONG_ADRS(0x28)#define DGA_CSR10_0 DGA001_BYTE_ADRS(0x28)#define DGA_CSR10_1 DGA001_BYTE_ADRS(0x29)#define DGA_CSR10_2 DGA001_BYTE_ADRS(0x2a)#define DGA_CSR10_3 DGA001_BYTE_ADRS(0x2b)#define DGA_CSR11 DGA001_LONG_ADRS(0x2c)#define DGA_CSR11_0 DGA001_BYTE_ADRS(0x2c)#define DGA_CSR11_1 DGA001_BYTE_ADRS(0x2d)#define DGA_CSR11_2 DGA001_BYTE_ADRS(0x2e)#define DGA_CSR11_3 DGA001_BYTE_ADRS(0x2f)#define DGA_CSR12 DGA001_LONG_ADRS(0x30)#define DGA_CSR13 DGA001_LONG_ADRS(0x34)#define DGA_CSR14 DGA001_LONG_ADRS(0x38)#define DGA_CSR15 DGA001_LONG_ADRS(0x3c)#define DGA_CSR16 DGA001_LONG_ADRS(0x40)#define DGA_CSR17 DGA001_LONG_ADRS(0x44)#define DGA_CSR18 DGA001_LONG_ADRS(0x48)#define DGA_CSR18_1 DGA001_BYTE_ADRS(0x49)#define DGA_CSR18_2 DGA001_BYTE_ADRS(0x4a)#define DGA_CSR18_3 DGA001_BYTE_ADRS(0x4b)#define DGA_CSR19 DGA001_LONG_ADRS(0x4c)#define DGA_CSR19_0 DGA001_BYTE_ADRS(0x4c)#define DGA_CSR19_1 DGA001_BYTE_ADRS(0x4d)#define DGA_CSR19_2 DGA001_BYTE_ADRS(0x4e)#define DGA_CSR19_3 DGA001_BYTE_ADRS(0x4f)#define DGA_CSR20 DGA001_LONG_ADRS(0x50)#define DGA_CSR21 DGA001_LONG_ADRS(0x54)#define DGA_CSR22 DGA001_LONG_ADRS(0x58)#define DGA_CSR23 DGA001_LONG_ADRS(0x5c)#define DGA_CSR24 DGA001_LONG_ADRS(0x60)#define DGA_CSR25 DGA001_LONG_ADRS(0x64)#define DGA_CSR26 DGA001_LONG_ADRS(0x68)#define DGA_CSR27 DGA001_LONG_ADRS(0x6c)/* * Interface Register (IFR) definitions. * * All registers of the IFR are accessible to both the local processor * and to other VMEbus masters. */#define DGA_IFR0 DGA001_LONG_ADRS(0x70)#define DGA_IFR1 DGA001_LONG_ADRS(0x74)#define DGA_IFR2 DGA001_LONG_ADRS(0x78)#define DGA_IFR3 DGA001_LONG_ADRS(0x7c)/************************************************************************** CSR0_0 0x00 0x00 local bus control **************************************************************************/#define CSR0_0_LBT_DIS 0x30 /* local bus time-out disable 5-4 */#define CSR0_0_LBT_256 0x20 /* local bus time-out 256 clks 5-4 */#define CSR0_0_LBT_128 0x10 /* local bus time-out 128 clks 5-4 */#define CSR0_0_LBT_64 0x00 /* local bus time-out 64 clks 5-4 */#define CSR0_0_TAOUTE 0x08 /* local bus TAOUT enable 3 *//************************************************************************** CSR0_1 0x00 0x01 bus error control and status **************************************************************************/#define CSR0_1_BERDYO 0x80 /* activate RDYO# upon bus error 7 */#define CSR0_1_LBTOUT 0x04 /* local bus time-out (status) 2 */#define CSR0_1_RQTOUT 0x02 /* request time-out (status) 1 */#define CSR0_1_VMEBERR 0x01 /* VMEbus bus error (status) 0 *//************************************************************************** CSR0_2 0x00 0x02 general purpose output enable **************************************************************************/#define CSR0_2_GPOE7 0x80 /* general purpose output 7 enable 7 */#define CSR0_2_GPOE6 0x40 /* general purpose output 6 enable 6 */#define CSR0_2_GPOE5 0x20 /* general purpose output 5 enable 5 */#define CSR0_2_GPOE4 0x10 /* general purpose output 4 enable 4 */#define CSR0_2_GPOE3 0x08 /* general purpose output 3 enable 3 */#define CSR0_2_GPOE2 0x04 /* general purpose output 2 enable 2 */#define CSR0_2_GPOE1 0x02 /* general purpose output 1 enable 1 */#define CSR0_2_GPOE0 0x01 /* general purpose output 0 enable 0 *//************************************************************************** CSR0_3 0x00 0x03 general purpose I/O **************************************************************************/#define CSR0_3_GPIO7 0x80 /* general purpose I/O 7 7 */#define CSR0_3_GPIO6 0x40 /* general purpose I/O 6 6 */#define CSR0_3_GPIO5 0x20 /* general purpose I/O 5 5 */#define CSR0_3_GPIO4 0x10 /* general purpose I/O 4 4 */#define CSR0_3_GPIO3 0x08 /* general purpose I/O 3 3 */#define CSR0_3_GPIO2 0x04 /* general purpose I/O 2 2 */#define CSR0_3_GPIO1 0x02 /* general purpose I/O 1 1 */#define CSR0_3_GPIO0 0x01 /* general purpose I/O 0 0 *//************************************************************************** CSR1_0 0x01 0x04 reset control and status **************************************************************************/#define CSR1_0_PURSTF 0x80 /* power-up reset (status) 7 */#define CSR1_0_RSWEN 0x40 /* reset switch enable 6 */#define CSR1_0_RSWSYS 0x20 /* VMEbus SYSRESET enable 5 *//************************************************************************** CSR1_1 0x01 0x05 system controller configuration **************************************************************************/#define CSR1_1_SYSCON 0x80 /* system controller (status) 7 */#define CSR1_1_RRS 0x10 /* round robin arbitration 4 */#define CSR1_1_PRI 0x00 /* prioritized arbitration 4 */#define CSR1_1_ARBT_DIS 0x0c /* arbitration time-out disable 3-2 */#define CSR1_1_ARBT_63 0x08 /* arbitration time-out 63 usec 3-2 */#define CSR1_1_ARBT_31 0x04 /* arbitration time-out 31 usec 3-2 */#define CSR1_1_ARBT_15 0x00 /* arbitration time-out 15 usec 3-2 */#define CSR1_1_SBT_DIS 0x03 /* VME bus time-out disable 1-0 */#define CSR1_1_SBT_511 0x02 /* VME bus time-out 511 usec 1-0 */#define CSR1_1_SBT_255 0x01 /* VME bus time-out 255 usec 1-0 */#define CSR1_1_SBT_127 0x00 /* VME bus time-out 127 usec 1-0 *//************************************************************************** CSR1_2 0x01 0x06 VMEbus requester control **************************************************************************/#define CSR1_2_DWB 0x80 /* VMEbus request 7 */#define CSR1_2_OWN 0x40 /* VMEbus request (status) 6 */⌨️ 快捷键说明
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