2选1多路选择器.vhd

Altera FPGA工程师成长手册源文件清华大学

LIBRARY IEEE;										//使用标准库
  USE IEEE.STD_LOGIC_1164.ALL;
  ENTITY mux21 IS										//实体定义
PORT (d0, d1,sel: IN bit;									//端口定义
       q: OUT bit);
END mux21;
ARCHITECTURE example OF mux21 IS
BEGIN
    PROCESS (d0,d1,sel)								//进程开始
    BEGIN
        IF sel='1'  THEN      
q<=d0;
        ELSE
          q<=d1;
        END IF;
    END PROCESS;
END example;