4选1多路选择器.vhd

来自「Altera FPGA工程师成长手册源文件清华大学」· VHDL 代码 · 共 26 行

LIBRARY IEEE;											//使用标准库
USE IEEE.std _logic_1164.ALL;
ENTITY mux41 IS										//实体定义
    PORT(d0:IN STD_LOGIC;								//端口定义
          d1:IN STD_LOGIC;
          d2:IN STD_LOGIC;
          d3:IN STD_LOGIC;
          sel:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
          q :OUT STD_LOGIC);
END mux41;
ARCHITECTURE rtl OF mux41 IS
BEGIN
    PROCESS(d0,d1,d2,d3,sel)
    BEGIN
       IF(sel="00") THEN
          q<=d0;
ELSIF(sel="01") THEN
  q<=d1;
          ELSIF(sel="10")THEN
              q<=d2;
          ELSE
              q<=d3;
          END IF;
    END PROCESS;
END rtl;