4阶滤波器.vhd

Altera FPGA工程师成长手册源文件清华大学

library ieee;
use ieee.std_logic_1164.all;
entity filter is
port ( clock	: in	std_logic;
	din0x	: in	std_logic_vector( 7 downto 0);
	coef0x	: in	std_logic_vector( 7 downto 0);
	din4x	: out	std_logic_vector( 7 downto 0);
coef4x	: out	std_logic_vector( 7 downto 0);
	result	: out	std_logic_vector(15 downto 0) );
end;
architecture rtl of filter is
component mult 
port (clock 	: in	std_logic;
	 a_in	: in	std_logic_vector( 7 downto 0);
	 b_in	: in	std_logic_vector( 7 downto 0);
	 a_out	: out	std_logic_vector( 7 downto 0);
	 b_out	: out	std_logic_vector( 7 downto 0);
	     r	: out	std_logic_vector(15 downto 0) );
end component;
component adder 
port	(clock	: in	std_logic;
	  r1x	: in	std_logic_vector(15 downto 0);
	  r2x	: in	std_logic_vector(15 downto 0);
	  r3x	: in	std_logic_vector(15 downto 0);
	  r4x	: in	std_logic_vector(15 downto 0);
	    y	: out	std_logic_vector(15 downto 0) ); 
end component;
signal coef1x,coef2x,coef3x,din1x,din2x,din3x:std_logic_vector(7 downto 0);
signal r0x,r1x,r2x,r3x: std_logic_vector(15 downto 0);
begin
mult_i0:mult  port map(clock,din0x,coef0x,din1x,coef1x,r0x);
mult_i1:mult  port map(clock,din1x,coef1x,din2x,coef2x,r1x);
	mult_i2:mult  port map(clock,din2x,coef2x,din3x,coef3x,r2x);
	mult_i3:mult  port map(clock,din3x,coef3x,din4x,coef4x,r3x);
	adder_i:adder port map(clock,r0x,r1x,r2x,r3x,result);
end;