sin_rom. vhd

Altera FPGA工程师成长手册源文件清华大学

LIBRARY IEEE;												//调用标准库文件
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 
ENTITY sinfsq IS
   PORT(												//端口定义
       clk : IN STD_LOGIC;
       dout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)) ;
END sinfsq;
ARCHITECTURE behavior OF sinfsq IS
COMPONENT sin_rom              								//声明ROM元件
	PORT(
		address	: IN	STD_LOGIC_VECTOR(5 DOWNTO 0);
		inclock	: IN 	STD_LOGIC;
		q	    : OUT	STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
   SIGNAL wt: STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
   PROCESS(clk)
   BEGIN
      IF clk'EVENT AND clk='1' THEN
         wt<=wt+1;
      END IF;
   END PROCESS;
   u1:rom_data PORT MAP(address=>wt,inclock=>clk,q=>dout);			//例化ROM元件
END behavior;