数控分频模块(speaker).vhd

Altera FPGA工程师成长手册源文件清华大学

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Speaker IS
PORT(CLK:IN STD_LOGIC;
Tone:IN INTEGER RANGE 0 TO 2047;
SPKS:OUT TD_LOGIC);
END Speaker;
ARCHITECTURE one OF peaker IS
SIGNAL PRECLK, FullSPKS: STD_LOGIC;
BEGIN
Divide16:PROCESS(clk)
VARIABLE Count: INTEGER RANGE 0 TO 15;
BEGIN
IF CLK'EVENT AND CLK='l'THEN  //将CLK进行16分频，PreCLK为CLK的16分频
Count4:=Count4+l;
IF Count=7 THEN 
PRECLK<='l';
ELSIF Count=15 THEN 
PRECLK<='0';
END IF;
END IF;
END PROCESS Divide16;
GenSpkS:PROCESS(PreCLK，Tone) //13位可预置计数器
VARIABLE Countl3: INTEGER RANGE 0 TO 2047;
BEGIN
IF PRECLK ' EVENT AND PRECLK='1' THEN
IF Countl3< Tone  THEN
Countl3:= Countl3+1;
FullSPkS<='l';
ELSE
Countl3:=0;
FullSpkS<='0';
END IF;
END IF;
END PROCESS;
Divide2:PROCESS(FulISPkS)//将输出再2分频，展宽脉冲，
VARIABLE Count2:STDLOGIC:
BEGIN
IF FullSPkS 'EVENT AND FullSPkS='1' THEN
Count2:=NOT Count2;
IF Count2='l' THEN
SPKS<='1';
ELSE
spks<='0';
END IF;
END IF;
END PROCESS;
END;