音乐节拍发生器music.vhd

Altera FPGA工程师成长手册源文件清华大学

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MUSIC IS
PORT ( clk4hz,auto:IN STD_LOGIC;
           ToneKey:IN STD_LOGIC_VECTOR(15 DOWNTO 0);
              Tone:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END MUSIC;
ARCHITECTURE one OF MUSIC IS
COMPONENT MUSICROM
PORT(address:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clock:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END COMPONENT;
SIGNAL Counter:  STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL Indexl:STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
P1: PROCESS(clk4hz)
BEGIN
IF Counter="10001001" THEN
Counter<="00000000";
ELSIF clk4hz ' EVENT AND clk4hz='1' THEN Counter<=Counter+1;
END IF;
END PROCESS P1;
ul: MUSICROM PORT MAP(address=>Counter,clock=>clk4hz,q=>Indexl);
P2: PROCESS(auto)
BEGIN
IF auto='0' THEN 
Tone<=ToneKey;
ELSE Tone <=Indexl;
END IF;
END PROCESS P2;
END one;