4个触发器构成的异步计数器.vhd

Altera FPGA工程师成长手册源文件清华大学

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DIFFR IS
PORT(CLK,CLR,D:IN STD_LOGIC;
      Q,QB:OUT STD_LOGIC);
END DIFFR;
ARCHITECTURE ART1 OF DIFFR IS
SIGNAL Q_IN:STD_LOGIC;
BEGIN
Q<=Q_IN;
QB<=NOT Q_IN;
PROCESS(CLK,CLR) 
BEGIN
IF(CLR='1')THEN
Q_IN<='0';
ELSIF (CLK'EVENT AND CLK='1')  THEN
Q_IN<=D;
END IF;
END PROCESS;
END ART1;                                           //以上描述一个D触发器,作为下面程序的一个元件
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY RPLCOUNT IS
PORT(CLK,CLR:IN STD_LOGIC;
             COUNT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END RPLCOUNT; 
ARCHITECTURE ART2 OF RPLCOUNT IS
SIGNAL COUNT_IN:STD_LOGIC_VECTOR(8 DOWNTO 0);   //说明将用到的内部信号
COMPONENT DFFR                                      //引用元件并说明其端口
          PORT(CLK,CLR,D:IN STD_LOGIC;
                Q,QB:OUT STD_LOGIC);
END COMPONENT;
BEGIN
COUNT_IN(0)<=CLK;
GEN1:FOR I IN 0 TO 3 GENERATE
U:DFFR PORT MAP(CLK=>COUNT_IN(I);             //元件例化并定义引脚连接关系
CLR=>CLR;
D=>COUNT_IN(I+1);
Q=>COUNT_IN(I);
QB=>COUNT_IN(I+1);
END GENERATE;
END ART2;