8位双向总线缓冲器.vhd

Altera FPGA工程师成长手册源文件清华大学

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY BI_DIR IS
    PORT(a,b:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
          en,dr:IN STD_STD_LOGIC); 
END BI_DIR;
ARCHITECTURE five OF BI_DIR IS							//结构体部分，用于电路功能描述
   SIGNAL Aout,Bout:STD_LOGIC_VECTOR(7 DOWNTO 0);   	//定义两个8位缓冲器，存储中间信号
BEGIN
One:PROCESS(a,en,dr)
BEGIN
IF en='0' AND  dr='1'THEN
Bout <=a;
ELSE
 Bout <"ZZZZZZZZ";
    END IF ;
b<= Bout;
END PROCESS;
Two:PROCESS(b,en,dr)
BEGIN
   IF en='0' AND  dr='1' THEN
Aout <=b;
   ELSE
Aout <"ZZZZZZZZ";
   END IF;
a<= Aout;
END PROCESS;
END five ;