3线-8线译码器.vhd

来自「Altera FPGA工程师成长手册源文件清华大学」· VHDL 代码 · 共 29 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DECODER IS								//实体部分，描述电路功能
PORT(a:IN STD_LOGIC_VECTOR(2 DOWNTO 0);		//定义端口
      g1,g2,g3: IN STD_LOGIC;
          y:OUT BIT_VECTOR (7 DOWNTO 0));
END DECODER;
ARCHITECTURE seven OF DECODER IS
BEGIN
PROCESS(a,g1,g2,g3)								//进程开始
BEGIN
    IF g1='0' THEN y<="11111111"; 
ELSIF g2='1' OR g3='1' THEN y<="11111111";
ELSE
CASE a IS
     WHEN  "000"=>Y(0)<= "11111110";
     WHEN  "001"=> Y(1) <="11111101";
     WHEN  "010"=> Y(2)<= "11111011";
     WHEN  "011"=> Y(3)<= "11110111";
     WHEN  "100"=> Y(4)<= "11101111";
     WHEN  "101"=> Y(5)<= "11011111";
     WHEN  "110"=> Y(6)<= "10111111";
     WHEN  "111"=> Y(7)<= "01111111";
     WHEN OTHERS=>"11111111";
    END CASE;
     END IF;
END PROCESS;
END seven;