1对4数据分配器.vhd

来自「Altera FPGA工程师成长手册源文件清华大学」· VHDL 代码 · 共 23 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;						//使用库
ENTITY DEMUX4_1 IS								//实体部分，描述电路
PORT(a:IN STD_LOGIC_VECTOR(1 DOWNTO 0);			//定义端口
     din: IN STD_LOGIC;
y0,y1,y2,y3:OUT STD_LOGIC);
END DEMUX4_1;									//结束实体部分
ARCHITECTURE nine OF DEMUX4_1 IS
BEGIN
PROCESS(a, y0,y1,y2,y3) 							//进程开始
BEGIN
     y0<='0';y1<='0';y2<='0';y3<='0';					
	CASE a IS									//CASE语句
		WHEN "00"=>y0<=din;
		WHEN "01"=>y1<= din;
		WHEN "10"=>y2<= din;
		WHEN "11"=>y3<= din;
	     WHEN others=>y<='0';
	END CASE;
	END IF;
END PROCESS;
END nine ;