模64计数器.vhd

Altera FPGA工程师成长手册源文件清华大学

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY updncount64 IS
PORT(Clk,clr,UPDOWN:IN STD_LOGIC;
qa,qb,qc,qd,qe,qf:OUT STD_LOGIC);//输出6位二进制数最大为63,所以是64进制计数器
End updncount64;                       
ARCHITECTURE ART OF updncount64 IS		//图5-4 加减计数器仿波形
Signal count_6:STD_LOGIC_VECTOR(5 DOWNTO 0);
Begin
qa= count_6(0); 
qb= count_6(1);
qc= count_6(2);
qd= count_6(3);
qe= count_6(4);
qf= count_6(5); 
process(clk,clr)
BEGIN
IF(clr='0')THEN      				
Count_6=000000;        
ELSIF(CLK'EVENT AND CLK='1')THEN    	-
IF(updn='1')THEN      	
Count_6= Count_6+1;
ELSE
Count_6= Count_6-1;  //为减1 计数器
END IF;
END IF;
END PROCESS;
END ART;